Bridge over troubled wrappers:automated interface synthesis

Abstract

System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often have different communication interfaces. We present an algorithm which automates the generation of provably correct HDL descriptions of interfaces between mismatched IP communication protocols. We significantly improve and extend existing work by providing a solution which addresses data mismatches, pipelining and differences in clock speeds. These ideas have been implemented and the tool has been used to synthesise wrappers and bridges for many SoC protocols.

Multi-clock Soc design using protocol conversion

“…A number of protocol conversion approaches for SoC have been proposed earlier [2,5,9]. In [5], a correct-byconstruction SoC design technique is presented.…”

“…In [5], a correct-byconstruction SoC design technique is presented. The work identifies precise conditions under which two IPs are compatible, and an automatic algorithm is used to generate an interface to make them compatible.…”

“…The work identifies precise conditions under which two IPs are compatible, and an automatic algorithm is used to generate an interface to make them compatible. A protocol conversion approach based on [5] is presented in [2]. The main contributions of this approach are the precise modelling of commercial bus protocols, a protocol conversion algorithm that always yields converters that can be translated to HDL, and converter sizes that are bounded by the size of the given protocols.…”

“…However, this approach generates converters for protocol pairs only and bridges data-width mismatches on an abstract level by avoiding unbounded data operations on any path in the converted system. Furthermore, both [5] and [2] are restricted to single-clock systems and as the notion of compatibility is limited to ensuring that IPs detect and respond to actions performed by each other, the approach cannot guarantee that a given system satisfied high-level functional specifications. Passerone et al [9] present a gametheoretic formulation for protocol conversion but no algorithm is provided, data or clock mismatches are not handled, and only uni-directional IP communication is allowed.…”

“…It shows that each technique uses different representations for protocols and algorithms to find a converter 1 . Furthermore, some approaches like [5] and [12] [6] does not allow converters to explicitly buffer control signals. The handling of data-width mismatches is limited in most existing approaches while none handle the conversion of multi-clock systems.…”