Built-in Self-Test and Defect Tolerance in Molecular Electronics-Based Nanofabrics

Wang, Z.; Chakrabarty, K.

doi:10.1007/978-0-387-74747-7_2

Cited by 3 publications

(3 citation statements)

References 21 publications

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“…The currently critical nanoscale manufacturing processes induce not negligible defect rates on all nanoscale computing systems, making the introduction of defect tolerant techniques mandatory as demonstrated in Wang and Chakrabarty [2007], Moritz et al [2007], Pulimeno et al [2013], Wang et al [2009], and Ahn et al [2009]. The abovementioned works tackle faults analysis and also defect tolerant architectures have been proposed, see for example [Bhaduri and Shukla 2004].…”

Section: Background and Perspectivesmentioning

confidence: 97%

Nanoarray architectures multilevel simulation

Frache

Graziano

Zamboni

2014

J. Emerg. Technol. Comput. Syst.

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Density and regularity are deemed as the major advantages of nanoarray architectures based on nanowires. Literature demonstrated that proper reliability analyzes must be performed and solutions have to be devised to improve nanoarrays yield. Their complexity and high-fault probability claim for specific design automation tools able to explore circuit solutions, performance and fault-tolerant approaches.We envision a simulator conceived to carry on characterizations in terms of logic behavior, defect-induced output error rate assessment, switching activity, power and timing performance. Though already existing for traditional technology, a simulator based on specific technological and topological tiled nanoarray descriptions, and conceived to join both device and architecture levels, has never been attempted at the degree of accuracy we present.Our contribution is twofold. First, marking a difference with respect to the state of the art, we developed an algorithm based on an event-driven engine which works at switch level and is not simply built on top of cost functions evaluations. The straightforward advantage is the possibility to follow the evolution of dynamic control sequences throughout all the inner components of the nanoarray, and, as a consequence, to obtain circuit level characterization as a projection of the real internal parameters.Second, we added to our simulator the capability to inject faults with specific statistical distributions associated to the nanoarray topology. Here we extract output error rates and yield for one of the possible nanoarray structures proposed in literature, the NASIC. Results specificity and accuracy demonstrate the simulator trustworthiness, its effectiveness for extensive nanoarrays characterization and its suitability as a foundation for both higher architectural and lower device simulation levels.The aim of this work, then, is to provide insights into the intertwined relation between actual technology and circuit design for these emerging fabrics, and, as a consequence, to clarify how defects and variability affect circuits and systems performance. ACM Reference Format:Frache, S., Graziano, M., and Zamboni, M. 2014. Nanoarray architectures multilevel simulation. ACM J.

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Section: Background and Perspectivesmentioning

confidence: 97%

Nanoarray architectures multilevel simulation

Frache

Graziano

Zamboni

2014

J. Emerg. Technol. Comput. Syst.

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“…Defect tolerance techniques have been proposed so that a DMFB is capable of performing assay operations even when there are defects on the biochip [ 41 ]. Generally in DMFBs, defect tolerance is realized by including redundant elements in the system to replace the faulty elements by using reconfiguration techniques.…”

Section: Testing Techniques For Conventional Digital Microfluidic mentioning

confidence: 99%

Advances in Testing Techniques for Digital Microfluidic Biochips

Shukla

Hussin

Hamid

et al. 2017

Sensors

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With the advancement of digital microfluidics technology, applications such as on-chip DNA analysis, point of care diagnosis and automated drug discovery are common nowadays. The use of Digital Microfluidics Biochips (DMFBs) in disease assessment and recognition of target molecules had become popular during the past few years. The reliability of these DMFBs is crucial when they are used in various medical applications. Errors found in these biochips are mainly due to the defects developed during droplet manipulation, chip degradation and inaccuracies in the bio-assay experiments. The recently proposed Micro-electrode-dot Array (MEDA)-based DMFBs involve both fluidic and electronic domains in the micro-electrode cell. Thus, the testing techniques for these biochips should be revised in order to ensure proper functionality. This paper describes recent advances in the testing technologies for digital microfluidics biochips, which would serve as a useful platform for developing revised/new testing techniques for MEDA-based biochips. Therefore, the relevancy of these techniques with respect to testing of MEDA-based biochips is analyzed in order to exploit the full potential of these biochips.

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“…Therefore either CMOS nano scale integration or future nano architectures no longer enjoy high reliability and it is needed to investigate fault tolerance techniques at different levels of abstraction to make the overall system reliable [2]. However, the overhead of these techniques should be taken into account to avoid reducing the gain of higher integration densities in current nano scale technologies and future nano architectures [3].…”

Section: Introductionmentioning

confidence: 99%

Reliability Analysis and Improvement in Nano Scale Design

Niknahad

Huebner

Becker

2010

2010 IEEE Computer Society Annual Symposium on VLSI

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According to the shrinking feature size of the VLSI circuits it is expected that nano scale devices and interconnections will introduce unprecedented level of defects and architectural designs need to settle with the uncertainty result at such scales. Several approaches for implementing the fault tolerance systems are already investigated. Most of these methods are applicable also in the case of high fault rates. Most protection methods are based on different redundancy methods which add extra detection and correction features to the design. We strongly believe that in future architectures it become more important assessing the fault tolerance techniques. Having an estimation of system fault tolerance can ensure critical applications working properly. In this work we propose a new method which checks reconfigurable architectures and during runtime finds violent spots in the design for probable transient and permanent failures. This approach is adjustable to either current FPGAs or future nano-architectures which are based on reconfigurability. We define a fault detection model for probable errors which uses an efficient algorithm that proves the fault tolerance in the reconfigurable architecture and computes a reliability factor for the architecture. This helps avoiding using the critical parts by future usages. Our method is applicable to different levels of granularity, such as gate level, logic block level, logic function level, unit level, etc. It is efficient and fast and can be simply integrated into the design flow.

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Built-in Self-Test and Defect Tolerance in Molecular Electronics-Based Nanofabrics

Cited by 3 publications

References 21 publications

Nanoarray architectures multilevel simulation

Nanoarray architectures multilevel simulation

Advances in Testing Techniques for Digital Microfluidic Biochips

Reliability Analysis and Improvement in Nano Scale Design

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