Buried CMOS Structure with a Straddle-Gate Architecture for Low Noise-Analog Applications

Abstract

A new buried-channel CMOS structure with a straddle-gate architecture is proposed in the present work. It can be carried out within the standard CMOS VLSI technological platform giving rise to both N- and P-type MOSFETs with buried channel. The main electrical features of the novel N-MOS transistor have been experimentally investigated. A significant lowering in 1/f noise and higher carrier mobility have been observed coherently with a bulk-like carrier transport due to the buried channel. The novel device would be promising for both analog and RF circuitry design.