Capacitance Boosting by Anti-Ferroelectric Blocking Layer in Charge Trap Flash Memory Device

Shin, Eui Joong; Shin, Sung Won; Lee, Seung Hwan; Lee, Tae In; Kim, Min Ju; Ahn, Hyun Jun; Kim, Jaehwan; Hwang, Wan Sik; Lee, Jae-Duk; Cho, Byung Jin

doi:10.1109/iedm13553.2020.9371984

Cited by 12 publications

(7 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For simulation, the comparator offset sampling and the quantization of partial sum in IMC-SRAM modeling were used to evaluate the network accuracy. In addition, we assumed that there is no impact of V TH variation since ISPP can minimize the distribution of V TH . The effect of the signed weight on network accuracy was evaluated under the same weight precision, the comparator offset sampling, and the quantization of partial sum.…”

Section: Resultsmentioning

confidence: 99%

“…In addition, we assumed that there is no impact of V TH variation since ISPP can minimize the distribution of V TH . 56 The effect of the signed weight on network accuracy was evaluated under the same weight precision, the comparator offset sampling, and the quantization of partial sum. Figure 5c shows the network accuracy of the signed/unsigned weight networks.…”

Section: Mac Operation For Signed Weight Computation Via the Fefet-pi...mentioning

confidence: 99%

See 1 more Smart Citation

Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Kim

et al. 2022

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

Ferroelectric field-effect transistors (FeFETs) have attracted enormous attention for low-power and high-density nonvolatile memory devices in processing-inmemory (PIM). However, their small memory window (MW) and limited endurance severely degrade the area efficiency and reliability of PIM devices. Herein, we overcome such challenges using key approaches covering from the material to the device and array architecture. High ferroelectricity was successfully demonstrated considering the thermodynamics and kinetics, even in a relatively thick (≥30 nm) ferroelectric material that was unexplored so far. Moreover, we employed a metal−ferroelectric−metal− insulator−semiconductor architecture that enabled desirable voltage division between the ferroelectric and the metal−oxide−semiconductor FET, leading to a large MW (∼11 V), fast operation speed (<20 ns), and high endurance (∼10 11 cycles) characteristics. Subsequently, reliable and energy-efficient multiply-and-accumulation (MAC) operations were verified using a fabricated FeFET-PIM array. Furthermore, a system-level simulation demonstrated the high energy efficiency of the FeFET-PIM array, which was attributed to charge-domain computing. Finally, the proposed signed weight MAC computation achieved high accuracy on the CIFAR-10 dataset using the VGG-8 network.

show abstract

Section: Resultsmentioning

confidence: 99%

Section: Mac Operation For Signed Weight Computation Via the Fefet-pi...mentioning

confidence: 99%

Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Kim

et al. 2022

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

show abstract

“…They found that the capacitance-boosting effect of the AFE layer increased MW and the operation speed without degrading the device performance. 163 Moreover, Ali et al boosted CT flash memory by replacing the charge-trapping layer with an AFE layer. 164 Figure 9d illustrates the effect of the trapping layer (dielectric, FE, or AFE) on the V th shift during the program/ erase operation and MW.…”

Section: Nonvolatile Semiconductor Devices 321 Induced Nonvolatility ...mentioning

confidence: 99%

“…adopted an AFE Hf 0.3 Zr 0.7 O 2 layer as the blocking layer in CTF memory. They found that the capacitance-boosting effect of the AFE layer increased MW and the operation speed without degrading the device performance . Moreover, Ali et al boosted CT flash memory by replacing the charge-trapping layer with an AFE layer …”

Section: Applications Of Fluorite-structured Antiferroelectricsmentioning

confidence: 99%

Emerging Fluorite-Structured Antiferroelectrics and Their Semiconductor Applications

Park

Lee

Choi

et al. 2023

ACS Appl. Electron. Mater.

View full text Add to dashboard Cite

The ferroelectric properties of fluorite-structured oxides have attracted significant attention from researchers because of their potential applications in nonvolatile memory devices, which are enabled by their compatibility with the complementary metal oxide semiconductor technology and physical scalability to a thickness below 10 nm. Another important emerging property of these materials is their antiferroelectricity, which originates from the field-induced transition between the polar and nonpolar phases. Various applications of fluorite-structured antiferroelectrics, such as those in volatile logic devices and cell capacitors for dynamic random-access memory, engineered nonvolatile memory, and energy storage/conversion devices, have been recently proposed, although they have not been investigated in detail compared to fluorite-structured ferroelectrics. The volatile nature of fluorite-structured antiferroelectrics with a characteristic field-induced phase transition, which clearly distinguishes them from ferroelectrics, have endowed these materials with unique properties that cannot be achieved by ferroelectrics. Therefore, the emerging antiferroelectricity of fluorite-structured oxides is comprehensively reviewed in this paper from its fundamentals to various semiconductor applications based on the existing literature.

show abstract

“…24,44,89,90 Reports indicate that the program/ erase endurance of FeFETs is already comparable to or even superior to that of CTF, owing to its program/erase mechanism that does not rely on electron tunneling. 39,88,91,92 However, a critical issue would be the disturbance expected during the program/erase. In NAND Flash, the cell transistors in the same string are serially connected, making it impossible to access individual cells simply by selecting the word line (WL) and bit line (BL).…”

mentioning

confidence: 99%

Hafnia-Based Ferroelectric Memory: Device Physics Strongly Correlated with Materials Chemistry

Choi,

Cho,

Kim

et al. 2024

J. Phys. Chem. Lett.

View full text Add to dashboard Cite

Figure 1. (a) Periodic array featuring a 1D crystallographic structure with a periodic arrangement of cations and anions, showcasing both an ideal distance (top panel) and a deviated distance from the ideal distance (lower panel). (b) The relationship between the coordination number and the relative ratio of the radii of cations and anions resulted from computational simulation. Reproduced with permission from ref 11. Copyright 2023 American Chemical Society. (c) Comparison table of the various crystallographic phases observed in (Hf,Zr)O 2 thin films. Reproduced under a CC BY 4.0 license from ref 8.

show abstract

Capacitance Boosting by Anti-Ferroelectric Blocking Layer in Charge Trap Flash Memory Device

Cited by 12 publications

References 2 publications

Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Power-Delay Area-Efficient Processing-In-Memory Based on Nanocrystalline Hafnia Ferroelectric Field-Effect Transistors

Emerging Fluorite-Structured Antiferroelectrics and Their Semiconductor Applications

Hafnia-Based Ferroelectric Memory: Device Physics Strongly Correlated with Materials Chemistry

Contact Info

Product

Resources

About