Challenges and Opportunities for High Performance 32 nm CMOS Technology

Sleight, J.W.; Lauer, Isaac; Dokumaci, O.; Fried, D.; Guo, Dechao; Haran, Bala; Narasimha, S.; Sheraw, C.; Singh, D.; Steigerwalt, Michael; Wang, X.; Oldiges, P.; Sadana, D. K.; Sung, C.Y.; Haensch, Wilfried; Khare, Mukesh

doi:10.1109/iedm.2006.346881

Cited by 44 publications

(8 citation statements)

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“…H IGH silicide-diffusion contact resistance R csd due to a large Schottky barrier (SB) height between NiSi and n-Si (100) has been identified as a major impediment to achieving continual improvement in the transistor performance beyond the 32-nm technology node [1], [2]. Fermi-level pinning at the NiSi/n-Si (100) interface sets the work function of NiSi to a midgap value of ∼4.7 eV.…”

Section: Introductionmentioning

confidence: 99%

Effective Schottky Barrier Height Reduction Using Sulfur or Selenium at the NiSi/n-Si (100) Interface for Low Resistance Contacts

Wong¹,

Chan²,

Samudra³

et al. 2007

IEEE Electron Device Lett.

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We explore a novel integration approach that introduces valence-mending adsorbates such as sulfur (S) or selenium (Se) by ion implantation and prior to nickel silicidation for the effective reduction of contact resistance and Schottky Barrier (SB) height at the NiSi/n-Si interface. While a low SB height of ∼0.12 eV can be obtained for NiSi formed on S-implanted n-Si, the insertion of a 1000 • C anneal prior to silicidation leads to S outdiffusion and loss of SB modulation effects. We demonstrate that Se-implanted Si does not suffer from Se outdiffusion even after a 1000 • C anneal, and subsequent Ni silicidation formed an excellent ohmic contact with a low SB height of 0.13 eV. Se segregation at the NiSi/n-Si (100) interface occurred. Implantation of Se and its segregation at the NiSi/n-Si interface is a simple and promising approach for achieving reduced SB height and contact resistance in future high-performance n-channel field-effect transistors.

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Section: Introductionmentioning

confidence: 99%

Effective Schottky Barrier Height Reduction Using Sulfur or Selenium at the NiSi/n-Si (100) Interface for Low Resistance Contacts

Wong¹,

Chan²,

Samudra³

et al. 2007

IEEE Electron Device Lett.

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“…The next step was annealing process to ensure all boron atoms being spread uniformly in the wafer at 900°C with nitrogen and followed by 950°C with dry oxigen. The next step was preparing the isolated neighboring transistor or Shallow Trench Isolator (STR) of 130 Å thicknesses [6]. Then, the wafer was oxidized with dry oxygen for 25 minutes at 900°C.…”

Section: Methodsmentioning

confidence: 99%

Effects of high-K dielectrics with metal gate for electrical characteristics of 18nm NMOS device

Atan

Ahmad

Majlis

2014

2014 IEEE International Conference on Semiconductor Electronics (ICSE2014)

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This paper presents a systematic study of various high-K materials on metal gate MOSFET for 18nm NMOS. From the study, we find a suitable combination materials between the high-K and metal gate, which has beneficial effects on the electrical characteristics of 18nm NMOS. The device shows a good improvement on its result of sub-threshold leakage current, I OFF, and drive current, I ON for different dielectric constants (k). The virtual design and fabrication of the device were performed by using Athena module. While electrical characteristic performance was simulated by using Atlas module of SILVACO software. Physical models of the 18nm NMOS were used for simulation from Al 2 O 3 , HfO 2 , and TiO 2 as the material gate dielectric, with TiSi 2 as the metal gate, which provide higher physical thickness that able to reduce the sub-threshold leakage current I OFF . Thus, excellent dielectric properties such as high-K constant, low I OFF , higher I ON , threshold voltage V TH , and electrical characteristics were demonstrated. From the simulation results of I ON and I OFF, it was proven that HfO 2 is the best dielectric material with combination of metal gate, TiSi 2 .

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“…Another effect of this smaller range between the low and high voltages required for the digital values becomes easier and faster. This might allow us to increase clock frequency to values that the older technologies were not able to sustain correctly [9][10].…”

Section: Synthesis In 500nm and 32nm Technologiesmentioning

confidence: 99%

“…All the simulations will be carried out with DC -Compiler from Synopsys. Finally, there will be a discussion of the results of technology scaling, as well as the changes we might expect for different optimizations approaches when creating an IC in a 32nm technology [9].…”

Section: Introductionmentioning

confidence: 99%

Implementation of 32nm MD5 Crypto-Processor using Different Topographical Synthesis Techniques and Comparison with 500nm Node

Jimenez

Borja

Silly

et al. 2021

2021 IEEE Fifth Ecuador Technical Chapters Meeting (ETCM)

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This work focuses on several synthetizations developed in both 32nm and 500nm technologies to evaluate the performance differences of MD5 Crypto-Processor. We decided to conduct a topographical synthesis instead of a nontopographical synthesis as it takes more parameters into account to create a more accurate design. We started by comparing some basic cells like inverters and register banks to understand the main differences between the two technologies. Several approaches were considered at this point to understand how different synthetization parameters affect the chip performance and characteristics. These different approaches were focused on time, power and area, and balanced configurations of synthesis flow. Finally, after comparing the performance given by the different approaches in basic digital structures, the balanced approach was implemented in 32nm and benchmarked with the 500nm implementation. Our conclusions were consistent among the various tests conducted and by downscaling we can expect a 10x increase in the clock frequency, a 100x decrease in power consumption, and around a 300x decrease in the area while using the 32nm technology. As a result, we developed a method to fairly compare complex systems to allow a designer to consider if the benefits justify the costs for a technology change.

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Challenges and Opportunities for High Performance 32 nm CMOS Technology

Cited by 44 publications

References 0 publications

Effective Schottky Barrier Height Reduction Using Sulfur or Selenium at the NiSi/n-Si (100) Interface for Low Resistance Contacts

Effective Schottky Barrier Height Reduction Using Sulfur or Selenium at the NiSi/n-Si (100) Interface for Low Resistance Contacts

Effects of high-K dielectrics with metal gate for electrical characteristics of 18nm NMOS device

Implementation of 32nm MD5 Crypto-Processor using Different Topographical Synthesis Techniques and Comparison with 500nm Node

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