Challenges for ultra-shallow junction formation technologies beyond the 90 nm node

Timans, P. J.; Lerch, W.; Niess, J.; Paul, S.; Acharya, N.; Nenyei, Z.

doi:10.1109/rtp.2003.1249120

Cited by 16 publications

(13 citation statements)

References 15 publications

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“…This gives us one discritized node equation for each node on the grid. The spatial derivative of temperature in equation (1) can be written as (4) and we can discritize the individual second spatial derivative terms. Let represent the anneal temperature at a node with co-ordinates (a,b).…”

Section: Chip Level Anneal Temperature Variation Analysismentioning

confidence: 99%

“…For example, the shallow p+-n junctions are difficult to fabricate due to high Boron diffusivity and formation of Boron channeling tail. Rapid Thermal Anneal (RTA) has been successfully used to address this problem [3,4]. RTA typically involves spike anneal, where the wafer is ramped to a high temperature and then allowed to cool immediately [5].…”

Section: Introductionmentioning

confidence: 99%

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Analyzing electrical effects of RTA-driven local anneal temperature variation

Joshi¹,

Agarwal²,

Sylvester³

et al. 2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Suppresing device leakage while maximizing drive current is the prime focus of semiconductor industry. Rapid Thermal Annealing (RTA) drives process development on this front by enabling fabrication steps such as shallow juction formation that require a low thermal budget. However, decrease in junction anneal time for more aggresive device scaling has reduced the characteristic thermal length to dimensions less than the typical die size. Also, the amount of heat transferred, and hence the local anneal temperature, is affected by the layout pattern dependence of optical properties in a region. This variation in local anneal temperature causes a variation in performance and leakage across the chip by affecting the threshold voltage (V th ) and extrinsic transistor resistance (R ext ). In this work, we propose a new local anneal temperature variation aware analysis framework which incorporates the effect of RTA induced temperature variation into timing and leakage analysis. We solve for chip level anneal temperature distribution, and employ TCAD based device level models for drive current (Ion) and leakage current (Ioff) dependence on anneal temperature variation, to capture the variation in device performance and leakage based on its position in the layout. Experimental results based on a 45nm experimental test chip show anneal temperature variation of up to ~10.5 o C, which results in ~6.8% variation in device performance and ~2.45X variation in device leakage across the chip. The corresponding variation in inverter delay was found to bẽ 7.3%. The temperature variation for a 65nm test chip was found to be ~8.65 o C.

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Section: Chip Level Anneal Temperature Variation Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Analyzing electrical effects of RTA-driven local anneal temperature variation

Joshi¹,

Agarwal²,

Sylvester³

et al. 2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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“…Intra-die thermal variation is due to local reflectivity variation associated with different microstructures [4]. An example of one test-chip that demonstrated such variation will be discussed here [5].…”

Section: Intra-die Thermal Variationmentioning

confidence: 99%

Impact of intra-die thermal variation on accurate MOSFET gate-length measurement

Ahsan

Schroder

Nowak

et al. 2009

2009 IEEE/SEMI Advanced Semiconductor Manufacturing Conference

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It is known that significant intra-die thermal absorption variation is caused by non-optimized rapid thermal anneal (RTA) conditions and the variation depends on the local pattern density of various types of exposed stacks of the wafer. This variation can create errors in the electrical measurement MOSFET gate length itself. Two electrical methods for measuring gate length will be discussed, namely, the resistive technique, where a long-wide poly-silicon resistor is used as a normalizing resistor; and the capacitive technique, where a long-wide plate gate capacitor is used as a normalizing capacitor. It is shown, that the capacitive technique is more immune to errors introduced by RTA driven intra-die thermal absorption variation. Methods of minimizing these measurement errors are briefly discussed.

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“…The well known example is pattern dependent Cu dishing and oxide erosion during Cu chemical mechanical polishing (CMP) process [23]. Rapid thermal anneal (RTA) process may also induce layout density dependent intra-die variations [24]. During RTA, local anneal temperature can vary across the die due to differences in radiation reflectivity of the layout patterns.…”

Section: Fig 8 Poly Density Induced Current Variabilitymentioning

confidence: 99%