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The solid phase epitaxial growth technique appears to be a promising method for achieving junction depths and sheet resistance values low enough to meet the performance specifications of the 65 and 45 nm node for boron, BF 2 , and BF 3 doping profiles in amorphous silicon. Room-temperature implants of these three dopant species into Si͑100͒ preamorphized by 74 Ge + ͑30 keV, 1.0 ϫ 10 15 cm −2 ͒ lead to boron concentration profiles that fulfill the technological requirements. It was found that even for ultrashallow junctions the time for the regrowth process at 650°C has to be optimized with regard to the implanted species in the range between 5 and 60 s, especially when fluorine is present. The thermal stability of the boron profile distribution that meets 65-nm-node requirements was evaluated by subsequent thermal anneals simulating the thermal effects expected for typical silicidation processes. For a more detailed investigation, the postannealing temperatures ranged from 250 to 1050°C with times from a few to several hundred seconds. All the junctions were analyzed by four-point probe and selected samples by secondary ion mass spectroscopy, transmission electron microscopy, and high-resolution electron microscopy.The combination of doping and activation technology is expected to provide solutions for highly activated, shallow, and abrupt dopant profiles required for advanced logic device technology beyond the 90-nm node. 1 In contrast to spike and/or flash annealing, a simple approach for the formation of ultrashallow junctions with boron consists of preamorphizing the substrate prior to dopant implantation followed by a low-temperature solid phase epitaxial growth process ͑SPEG͒. The SPEG technique currently appears to be a promising method for achieving junction depth and sheet resistance values low enough to meet the performance specifications for the 65-and 45-nm node. The optimal process for high activation during SPEG involves annealing at ϳ650°C for 5-60 s in an inert ambient. 2 The main advantages of the SPEG technique is that it has been extensively studied for at least three decades. In general it is rather simple and requires only conventional implant and rapid thermal processing equipment. It is also a low-temperature approach that is thermally compatible with advanced materials such as high-k dielectrics and metal gates. In this paper we present some of our recent results on the formation of ultrashallow junctions using the SPEG technique. Additionally, data for technology nodes beyond 90 nm are also presented in a sheet resistance vs junction depth matrix, including data from current literature of various techniques.However, the thermal stability of activated junctions is a critical consideration for front-end complementary metal oxide semiconductor ͑CMOS͒ manufacturing. Therefore, in the second part we present a detailed study of boron deactivation during thermal processes after SPEG. Postannealing temperatures were chosen in order to "simulate" typical self-aligned silicide processes for NiSi or...

Ion implants of 1.0 keV 11B+, 5 keV BF 2+, and 2.0 keV As+ at a dose of IeI5/cm2 were rapid thermal annealed (RTA) in a STEAG AST-2800µ with varying percents of oxygen in N2, ranging from 0-lppm to 50,000 ppm to investigate the effects of low concentrations of oxygen during anneal. Sheet resistance (Rs), ellipsometry, SIMS, Tapered Groove Profilometry (TGP), and Scanning Force Microscopy (SFM) were employed to characterize these layers. For each of these implant cases, an optimal RTA condition is established which maximizes retained dose while still producing shallow junctions. As a function of O2 content, anneal temperature and implant condition, three regimes are observed that affect after anneal retained dose. These regimes are: dopant loss to the ambient resulting from etching of Si, dopant loss by out-diffusion from evaporation/chemical reactions, a capping regime that minimizes out-diffusion. In this later regime the dopant loss results from consumption into the RTA grown oxide. In addition, this paper also discusses oxidation enhanced diffusion (OED) and identifies its extent as a function of temperature and O2 content of the anneal for the three implant conditions investigated. For example, a 1.0 keV 11B+wafer annealed at 1050°C lOs in a controlled 33 ppm of O2 in N2 yields a SIMS junction depth 320 Å shallower than previously reported by others.

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