Channel length dependence of hot-carrier-induced degradation in n-type drain extended metal-oxide-semiconductor transistors

Chen, Jone-Fang; Chen, Shiang Yu; Wu, Kaijie; Liu, C. M.

doi:10.1063/1.3040693

Cited by 9 publications

(2 citation statements)

References 4 publications

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“…As it was repeatedly discussed in the literature, not only the amount of interface traps generated during the stress is important but also their spatial distribution, see e.g. [26,27]. Moreover, the device life-time may be estimated using different device characteristic degradation, e.g.…”

Section: Devicesmentioning

confidence: 99%

“…the threshold voltage, transconductance and linear drain current, etc. But the prevalent portion of degradation of different parameters is controlled by traps located in different position along the interface [26,27]. For this reason, it is worth plotting also R SP,max integrated along the SiO 2 /Si interface and proportional to the total amount of damage, see Fig.…”

Section: Devicesmentioning

confidence: 99%

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Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

Starkov

Tyaginov

Triebl

et al. 2010

2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

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Using a physics-based model for hot-carrier degradation we analyze the worst-case conditions for long-channel transistors of two types: a relatively low voltage n-MOSFET and a highvoltage p-LDMOS. The key issue in the hot-carrier degradation model is the information about the carrier energetical distribution function which allows us to asses the carrier acceleration integral determining the interface state build-up and which controls the interplay between the single-and multiple-carrier mechanisms of Si-H bond rupture. To analyze the worst-case conditions we generate intensity maps, i.e. dependences of some crucial quantities on source-drain Vds and gate Vgs stress voltage. These quantities are the boundary of the high-energy tail of the energy distribution function, the interface state generation rate and the total dose of degradation. The difference between positions of severest degradation spots evaluated according different criteria is also plotted as a function of stress voltages. Using these maps we demonstrate that the worst-case conditions are realized at 0.4Vds < Vgs < 0.5Vds for the n-MOSFET and at the maximal gate current for p-LDMOS. These findings correspond to experimental results published in the literature.

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Section: Devicesmentioning

confidence: 99%

Section: Devicesmentioning

confidence: 99%

Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

Starkov

Tyaginov

Triebl

et al. 2010

2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

View full text Add to dashboard Cite

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Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

Liu

Zhang

Sun

et al. 2014

Applied Physics Letters

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Anomalous output characteristic shift of the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer is investigated. It shows that the linear drain current has obvious decrease when the output characteristic of fresh device is measured for two consecutive times. The charge pumping experiments demonstrate that the decrease is not from hot-carrier degradation. The reduction of cross section area for the current flowing, which results from the squeezing of the depletion region surrounding the P-top layer, is responsible for the shift. Consequently, the current capability of this special device should be evaluated by the second measured output characteristic.

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Hot-carrier-induced linear drain current and threshold voltage degradation for thin layer silicon-on-insulator field P-channel lateral double-diffused metal-oxide-semiconductor

Zhou

Qiao

et al. 2015

Applied Physics Letters

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Hot-carrier-induced linear drain current (Idlin) and threshold voltage (Vth) degradations for the thin layer SOI field p-channel lateral double-diffused MOS (pLDMOS) are investigated. Two competition degradation mechanisms are revealed and the hot-carrier conductance modulation model is proposed. In the channel, hot-hole injection induced positive oxide trapped charge and interface trap gives rise to the Vth increasing and the channel conductance (Gch) decreasing, then reduces Idlin. In the p-drift region, hot-electron injection induced negative oxide trapped charge enhances the conductance of drift doping resistance (Gd), and then increases Idlin. Consequently, the eventual Idlin degradation is controlled by the competition of the two mechanisms due to conductance modulation in the both regions. Based on the model, it is explained that the measured Idlin anomalously increases while the Vth is increasing with power law. The thin layer field pLDMOS exhibits more severe Vth instability compared with thick SOI layer structure; as a result, it should be seriously evaluated in actual application in switching circuit.

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Channel length dependence of hot-carrier-induced degradation in n-type drain extended metal-oxide-semiconductor transistors

Cited by 9 publications

References 4 publications

Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

Analysis of worst-case hot-carrier conditions for high voltage transistors based on full-band monte-carlo simulations

Anomalous output characteristic shift for the n-type lateral diffused metal-oxide-semiconductor transistor with floating P-top layer

Hot-carrier-induced linear drain current and threshold voltage degradation for thin layer silicon-on-insulator field P-channel lateral double-diffused metal-oxide-semiconductor

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