Characteristic Enhancement of Hetero Dielectric DG TFET Using SiGe Pocket at Source/Channel Interface: Proposal and Investigation

Sahu, Sushree Anusmita; Goswami, Rupam; Mohapatra, Sushanta Kumar

doi:10.1007/s12633-019-00159-9

Cited by 27 publications

(4 citation statements)

References 17 publications

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“…Vth is the gate voltage at which the device starts conducting. It's essential for determining the operating region of the TFET (24). To analyze the drain current (Id) varies with different gate-source voltages.…”

Section: Resultsmentioning

confidence: 99%

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Buttol,

Balaji,

Srinivasa Rao

2024

IJE

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In this work, a Symmetrical Dual Gate Tunnel Field Effect Transistor (SDGTFET) is proposed with gate dielectric materials in 10nm technology. The electrical performance parameters of this proposed device are investigated using technology computer aided design (TCAD) simulator. The new SDGTFET employing with high-k dielectric material such as hafnium oxide (HfO2) and interfacial layer (IL). The 2nm HfO2 with 30 dielectric constant is used between the interfacial layer and the metal gate on both sides of the device. The variation of the drain current with the varying of gate length, effective gate materials and effective oxide layer thickness of the device is evaluated in this work. By optimizing the proposed device with gate dielectric material the on current gets ∼4.2 times enhanced and the averaged subthreshold swing (SSavg) becomes reduced from 90.2 mV/dec to 53.8 mV/dec. Therefore, the SDGTFET structure has better performance than single material and double material TFET and shows a lower ambipolar current and a better on current to off current ratio.

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Section: Resultsmentioning

confidence: 99%

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Buttol,

Balaji,

Srinivasa Rao

2024

IJE

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“…This aids in fine-tuning the design parameters for optimal performance. Therefore, the proposed device design of DMG-FinFET with high-K dielectric materials, engineers can create transistors that offer improved qualitative performance, reduced power consumption, and enhanced reliability for advanced semiconductor technologies (25,26). High-K dielectric materials and the FinFET architecture help achieve lower subthreshold slopes, reducing power consumption in subthreshold slop operation (27).…”

Section: Figure 1 Proposed Dmg-finfetmentioning

confidence: 99%

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Padmaja,

Vemana Chary,

Erigela

et al. 2024

IJE

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A High-K Dielectric Dual Metal Gate FinFET (DMG-FinFET) is proposed in this work to improve the drain current and electrical characteristics of the device. The proposed device employing dielectric materials such as Silicon dioxide, Hafnium oxide and Titanium oxide and investigated in 10 nm technology. The architecture represents a critical advancement in transistor design, addressing challenges posed by traditional high-K gate dielectric materials being HfO2 and TiO2. This work employs a comprehensive approach, incorporating simulation techniques to evaluate the performance metrics of DMG FinFET. This investigation encompasses key aspects being transistor characteristics, power consumption, and reliability. This high-k dielectric (HfO2) Dual material Gate -FinFET device achieving improved performance parameters such as Ion= 32.12 mA, Ioff= 33 μA, Gm(max) = 0.045 S, Gds(max) = 0.024 S and Ron(max) = 32.87 kΩ. Therefore this work is suitable for designing high performance devices with high-k dielectric materials being HfO2 and TiO2. The impact of dual metal gate materials on Ion, Ioff, Gm (max), Gds(max) and Ron(max) is calculated and improved 64% compared to conventional device.

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“…Consequently, the carriers near the bottom of the channel experience a lateral movement, resulting in the flow of drain current. Consequently, the improved drain current predominantly flows in the lower region of the channel (25,26). Consequently, the proposed device exhibits several advantages, including maximum velocity, the highest electron density, an effective channel depth, and optimal drain current flow in the channel.…”

Section: Drain Current Characteristicsmentioning

confidence: 99%

Gate Oxide Thickness and Drain Current Variation of Dual Gate Tunnel Field Effect Transistor

Howldar,

Balaji,

Srinivasa Rao

2024

IJE

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Characteristic Enhancement of Hetero Dielectric DG TFET Using SiGe Pocket at Source/Channel Interface: Proposal and Investigation

Cited by 27 publications

References 17 publications

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Design and Analysis of Symmetrical Dual Gate Tunnel Field Effect Transistor with Gate Dielectric Materials in 10nm Technology

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Gate Oxide Thickness and Drain Current Variation of Dual Gate Tunnel Field Effect Transistor

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