Characteristics of Recessed-Gate TFETs With Line Tunneling

Lin, Jyi-Tsong; Wang, Tzu-Chi; Lee, Wei-Han; Yeh, Chih-Ting; Glass, Stefan; Zhao, Qing‐Tai

doi:10.1109/ted.2017.2786215

Cited by 28 publications

(13 citation statements)

References 15 publications

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“…All in all, these results demonstrate that in order to improve the dynamic performance of TFETs, their on-current must be increased, and the question arises as to how such an improvement can be achieved [76]. Studies have shown that innovative architectures of TFETs, such as those using line tunneling and hetero-structures, increase the potential to achieve a higher Ion [92]. Hence, in the following the effect of line-tunneling is implemented in the compact model and inspected.…”

Section: Universitat Rovira I Virgili Compact Modeling Of Intrinsic Cmentioning

confidence: 80%

See 1 more Smart Citation

Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs

Farokhnejad

Graef

Horst

et al. 2017

2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

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ADVERTIMENT. L'accés als continguts d'aquesta tesi doctoral i la seva utilització ha de respectar els drets de la persona autora. Pot ser utilitzada per a consulta o estudi personal, així com en activitats o materials d'investigació i docència en els termes establerts a l'art. 32 del Text Refós de la Llei de Propietat Intel•lectual (RDL 1/1996). Per altres utilitzacions es requereix l'autorització prèvia i expressa de la persona autora. En qualsevol cas, en la utilització dels seus continguts caldrà indicar de forma clara el nom i cognoms de la persona autora i el títol de la tesi doctoral. No s'autoritza la seva reproducció o altres formes d'explotació efectuades amb finalitats de lucre ni la seva comunicació pública des d'un lloc aliè al servei TDX. Tampoc s'autoritza la presentació del seu contingut en una finestra o marc aliè a TDX (framing). Aquesta reserva de drets afecta tant als continguts de la tesi com als seus resums i índexs.

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Section: Universitat Rovira I Virgili Compact Modeling Of Intrinsic Cmentioning

confidence: 80%

“…Bearing in mind the fact that with further innovation of the structures, the TFET on-current can be enhanced, the I ds [92], further circuit simulations are carried out to observe the behavior After all mentioned above and considering the results of the circuit simulation, the following can be concluded:…”

Section: Sg Line Tunneling Tfet-based Circuitsmentioning

confidence: 99%

Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs

Farokhnejad

Graef

Horst

et al. 2017

2017 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)

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“…High switching ratio ( I ON / I OFF ) can be obtained due to the large on-state current ( I ON ) and small off-state current ( I OFF ) provided by the line tunneling junction. Furthermore, the application of a fin structure in DF-TFET can remarkably reduce the footprint compared to the planer line tunneling TFET [ 30 , 31 ]. Figure 1 b shows an available fabrication flow to form the structure of DF-TFET.…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

et al. 2020

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In this paper, a dopingless fin-shaped SiGe channel TFET (DF-TFET) is proposed and studied. To form a high-efficiency dopingless line tunneling junction, a fin-shaped SiGe channel and a gate/source overlap are induced. Through these methods, the DF-TFET with high on-state current, switching ratio of 12 orders of magnitude and no obvious ambipolar effect can be obtained. High κ material stack gate dielectric is induced to improve the off-state leakage, interface characteristics and the reliability of DF-TFET. Moreover, by using the dopingless channel and fin structure, the difficulties of doping process and asymmetric gate overlap formation can be resolved. As a result, the structure of DF-TFET can possess good manufacture applicability and remarkably reduce footprint. The physical mechanism of device and the effect of parameters on performance are studied in this work. Finally, on-state current (ION) of 58.8 μA/μm, minimum subthreshold swing of 2.8 mV/dec (SSmin), average subthreshold swing (SSavg) of 18.2 mV/dec can be obtained. With improved capacitance characteristics, cutoff frequency of 5.04 GHz and gain bandwidth product of 1.29 GHz can be obtained. With improved performance and robustness, DF-TFET can be a very attractive candidate for ultra-low-power applications.

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“…These are the main disadvantages for TFETs [2]. So some novel TFET structures have been designed to solve this problem, such as U-shaped channel TFET, T-shaped gate TFET (TGTFET), heterojunction TFET and so on [3][4][5][6][7]. And Some improved devices have achieved good results, Such as TGTFET.…”

Section: Introductionmentioning

confidence: 99%

A T-shaped gate tunneling field effect transistor with negative capacitance, super-steep subthreshold swing

Jia

Pan

et al. 2021

Nanotechnology

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With the development of semiconductor technology, the size of traditional metal oxide semiconductor field effect transistor devices continues to decrease, but it cannot meet the requirements of high performance and low power consumption. Low power tunneling field effect transistor (TFET) has gradually become the focus of researchers. This paper proposes a novel T-shaped gate TFET based on the silicon with the negative capacitance (NC-TGTFET). On the basis of TGTFET, ferroelectric material (HZO) is used as gate dielectric. The simulation results show that, compared with the traditional TGTFET, the opening order and sensitivity of the two tunneling junctions are different. The influences of thickness and the doping concentration of pocket and ferroelectric material properties on the characteristics of NC-TGTFET is also discussed by Sentaurus simulation tool. Furthermore, the negative capacitance of ferroelectric material makes NC-TGTFET have a very steep subthreshold swing (18.32 mV/dec) at the range of drain current from 1×10 −15 to 1×10 −7 A μm −1 . And the on-state current (V g = 0.5 V, V d = 0.5 V) is 1.52×10 −6 A μm −1 .

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Characteristics of Recessed-Gate TFETs With Line Tunneling

Cited by 28 publications

References 15 publications

Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs

Compact modeling of intrinsic capacitances in Double-Gate Tunnel-FETs

A Novel Dopingless Fin-Shaped SiGe Channel TFET with Improved Performance

A T-shaped gate tunneling field effect transistor with negative capacitance, super-steep subthreshold swing

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