Characteristics of Sn–Cu Solder Bump Formed by Electroplating for Flip Chip

Jung, Seung-Boo; Jung, Jae Pil; Zhou, Yunhong

doi:10.1109/tepm.2005.863266

Cited by 23 publications

(11 citation statements)

References 16 publications

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“…The Sn deposits without a PR The morphologies of the fabricated Sn bumps without a PR mould (Fig. 4) showed a rougher periphery and top surface compared to those of a Sn [20] and a Sn-Cu bump [11] formed with a PR mould. After the reflow, however, the electroplated bumps became round with smooth surfaces; thus, the rough surface with facets may no longer be an important issue.…”

Section: Resultsmentioning

confidence: 99%

“…The bump shape is similar to the shape of a rivet head but without a columnar part under the head. The columnar part of the bump appears commonly in conventional mushroom bumps produced with a PR mould [11]. In Fig.…”

Section: Electroplating Of the Sn Bumpsmentioning

confidence: 99%

“…Many prior studies related to this method have been conducted [5,6,[9][10][11][12][13]. Much interest has been generated by lead-free Sn-based alloys as bumping materials, and Sn-Ag [5,10,[12][13][14][15][16][17], Sn-Cu [11], and Sn-Ag-Cu [18,19] electroplating approaches have been investigated. In this study, pure Sn was selected as a bumping material because Sn provides a uniform composition of all of the created bumps, with leads to easier electroplating conditions.…”

Section: Introductionmentioning

confidence: 99%

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New process of electroplate Sn bumping on TSV without a PR mould for 3D-chip stacking

et al. 2011

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A new method of fabricating Sn bumps by electroplating without a PR (photoresist) mould on a Si die was investigated in terms of the bump growth and morphology for application to 3D-chip stacking. The omission of the PR mould was expected to result in a reduction of the process time and of the cost of electroplate bumping on the Si chip. For the electroplating of Sn bumps, a cathode consisting of a Si die with a Cuplugged TSV (through-silicon via) was used, with Sn or Pt adopted as an anode. The current densities and plating times were varied to assess the change in the Sn bump size and morphology. As a result, Sn bumps with rivet-head shapes were successfully fabricated via electroplating on Cu-plugged TSV without a PR mould. The height and width of the Sn bump were increased at a longer plating time and a larger current density. The Sn or Pt anode had a minimal effect on the electroplating results: The deposition rates and morphologies of the Sn bumps with different anodes were nearly identical in the range from 15 to 60 min at −30 mA/cm 2 . The Sn deposit without a PR mould developed a facet with various directions less than 5 min of plating time. After 15 min, however, the selective growth of some facets became dominant, which enlarged the preferred facets and caused a decrease in the number of facets.

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Section: Resultsmentioning

confidence: 99%

Section: Electroplating Of the Sn Bumpsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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New process of electroplate Sn bumping on TSV without a PR mould for 3D-chip stacking

et al. 2011

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“…Meanwhile, the electroplated bumps are generally produced using a photoresist (PR) mould established by lithography [9]. This lithography step adds to the processing time and cost considerably [10], [11]. In addition, consistent composition and correct size of the solder bump are difficult to obtain by the electroplating method [10].…”

Section: Introductionmentioning

confidence: 99%

Non-PR Sn-3.5Ag Bumping on a Fast Filled Cu-Plug by PPR Current

Hong

Jung

Lee

et al. 2013

IEEE Trans. Compon., Packag. Manufact. Technol.

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The electroplating of Sn-3.5 wt% Ag bumps without a photoresist (PR) mould on a Si chip was performed to reduce the production steps and cost for 3-D chip stacking. The electroplating characteristics of Sn-Ag and Sn-Ag bump growth were examined. The Sn-Ag bumps were electroplated on the Cuplugged TSVs (through-silicon vias) of a Si chip. The Cu plug in the via was produced using a high-speed Cu filling process by a periodic pulse reverse current waveform. The electroplating current was supplied to the exposed Cu surface in the TSVs to produce the Sn-3.5Ag bumps. As the experimental results show, the Sn-3.5Ag bumps were fabricated successfully without a PR mould, with no serious defects by electroplating. The Ag contents in the Sn-Ag bump decreased with increasing current density. Besides, the bump height and width increased with increasing plating time. The bump width grew isotropically because of the absence of a PR mould. The Sn-3.55 wt% Ag bumps were obtained at a current density of −55 mA/cm 2 for 20 min on the Cu plugs.Index Terms-3-D packaging, electroplating, photoresist mould, Sn-3.5Ag bump, through-silicon via.

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“…As a bumping method, electroplating is considered to be a suitable process due to its efficiency in fabricating smaller sized and narrower pitched bumps. 20) Electroplating processes for solder bumps generally employ a photo-resist-mold (PRM) on a Si wafer [20][21][22][23][24][25][26] to confine the cathode surface area and control the shape of the deposits. However, applying a PRM requires a series of processes; PR coating, ultra-violet (UV) exposure, development and PR removal, which involve extra time and cost.…”

Section: Introductionmentioning

confidence: 99%

A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging

et al. 2010

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A new bumping process on a Si die by electroplating without a photo-resist-mold (PRM) was assessed for the three dimensional (3D) stacking of Si dice. In this process, solder bumps were deposited selectively onto the surface of a Cu plugged-through silicon-via (TSV) in a Si die. Since lithography related processes to make a PRM for solder bumping were omitted, it can reduce the production time and cost for bumping. The substrate was a Si wafer, and TSVs were produced by deep-ion-reactive-etching (DRIE). As an insulation layer, SiO 2 was formed by high-density-plasma-chemical-vapor-deposition (HDPCVD) or wet oxidation method. A Ti adhesion and an Au seed layers were deposited by sputtering. Cu was plugged into the vias by pulsed direct-current (DC) electroplating. The backside of the Si wafer was ground by chemicalmechanical-polishing (CMP). Sn bumps were electroplated on the Cu plugged vias by a current supplied through a Cu-overplated layer (COL) on the vias surface. As experimental results, wet oxidation provided a uniform SiO 2 thickness through the via depth, whereas the SiO 2 thickness by HDPCVD decreased with the via depth. The Ti and Au thicknesses also decreased along the via depth. In electroplating for Cu plugging, defect-free Cu plug was achieved by pulsed DC for 18 h, where one cycle composed of a 5 s cathodic term with À12:2 mAÁcm À2 and a 25 s anodic term with 2.3 mAÁcm À2 . Sn bumping using COL without PRM was accomplished successfully at a current density of À30 mAÁcm À2 for 15 min. The diameter and height of the Sn bumps ranged from 48.5 to 52 mm and 22 to 25 mm, respectively. The bumps had a rivet head shape without a columnar part and showed facets on the bump surface. The COL was removed by CMP without damage to the bumps.

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Characteristics of Sn–Cu Solder Bump Formed by Electroplating for Flip Chip

Cited by 23 publications

References 16 publications

New process of electroplate Sn bumping on TSV without a PR mould for 3D-chip stacking

New process of electroplate Sn bumping on TSV without a PR mould for 3D-chip stacking

Non-PR Sn-3.5Ag Bumping on a Fast Filled Cu-Plug by PPR Current

A New Non-PRM Bumping Process by Electroplating on Si Die for Three Dimensional Packaging

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