Characterization of Negative-Bias Temperature Instability of Ge MOSFETs With &lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;${\rm GeO}_{2}/{\rm Al}_{2}{\rm O}_{3}$ &lt;/tex-math&gt;&lt;/inline-formula&gt; Stack

Ma, Jun; Zhang, Chenglong; Ji, Zhigang; Benbakhti, B.; Zhang, Wensheng; Zheng, Xiaolong; Mitard, J.; Kaczer, B.; Groeseneken, G.; Hall, Steve; Robertson, John; Chalker, Paul R.

doi:10.1109/ted.2014.2314178

Cited by 9 publications

(2 citation statements)

References 60 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Taguchi method uses the signal-to-noise ratio (SNR) as the quality characteristic of choice. The SNR characteristics are divided into three distinct categories for which the characteristics are continuous, 32 and is expressed in (1), (2), and (3), respectively, where n is the number of observations and y is the observed data. The average data, ŷ is expressed in (4) while the variance, s 2 y is expressed in (5):…”

Section: Methodology Of Device Optimizationmentioning

confidence: 99%

“…1 This has encouraged the development of silicon-based metal-oxide-semiconductor field effect transistor (Si-MOSFET) downscaling which has exceeded expectations with the continuous increase in chip density as well as operation speed since 1960s. 2,3 However, this successful downscaling has approached its end as the features sizes reaches its' limits which can no longer shrunk down beyond a certain small dimensions due to severe short channel effects (SCEs). 4 For instance, as one of the SCEs, hot carrier aging becomes intolerably enhanced as device channel lengths are scaled down, 5,6 in which can severely degrade the device performances.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Optimization of 7 nm Strained Germanium FinFET Design Parameters Using Taguchi Method and Pareto Analysis of Variance

Othman

Azhari

Hatta

et al. 2018

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

FinFET technology has emerged as an excellent alternative to planar MOSFET for sub-nanometer scaled technology processes in order to achieve high performance and low power. The geometrical parameters of FinFET are particularly sensitive to the devices' figure-of-merits. In this work, the effects of critical geometrical factors of the 7 nm strained germanium FinFET were systematically investigated by studying the resulting I-V characteristics, DIBL, and subthreshold swing. Variation of structure parameters are implemented and optimized using the Taguchi method signal-to-noise ratio with orthogonal arrays of L 27 (3 13 ) as well as Pareto analysis of variance to obtain the best combinations of parameters for each response performance. The results reveals that the nominal threshold voltage achieved for n-FinFET and p-FinFET are 0.146V and −0.152V respectively. It was observed that design variations were shown to affect n-FinFET more compared to p-FinFET. Drive current can be increased up to approximately 22% for an optimized I on performance, while leakage can be reduced up to 10 3 in I off optimization. Moreover, it is also observed from the Pareto analysis that the performance of FinFET is mainly affected by the dominant factors of fin length, top fin width, and the interaction of both for n-and p-FinFET by more than 50% for each response.

show abstract

Section: Methodology Of Device Optimizationmentioning

confidence: 99%

mentioning

confidence: 99%

Optimization of 7 nm Strained Germanium FinFET Design Parameters Using Taguchi Method and Pareto Analysis of Variance

Othman

Azhari

Hatta

et al. 2018

ECS J. Solid State Sci. Technol.

View full text Add to dashboard Cite

show abstract

Impact of Channel, Stress-Relaxed Buffer, and S/D Si1−xGe x Stressor on the Performance of 7-nm FinFET CMOS Design with the Implementation of Stress Engineering

Othman

Hatta

Soin

2018

Journal of Elec Materi

View full text Add to dashboard Cite

Oxygen vacancy defect engineering using atomic layer deposited HfAlOx in multi-layered gate stack

Bhuyian

Sengupta²,

Vurikiti³

et al. 2016

Applied Physics Letters

View full text Add to dashboard Cite

This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlOx with extremely low Al (<3% Al/(Al + Hf)) incorporation in the Hf based high-k dielectrics. The defect activation energy estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V+/V2+, are the primary source of defects in these dielectrics. When Al is added in HfO2, the V+ type defects with a defect activation energy of Ea ∼ 0.2 eV modify to V2+ type to Ea ∼ 0.1 eV with reference to the Si conduction band. When devices were stressed in the gate injection mode for 1000 s, more V+ type defects are generated and Ea reverts back to ∼0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO2 contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.

show abstract

Characterization of Negative-Bias Temperature Instability of Ge MOSFETs With <inline-formula> <tex-math notation="TeX">${\rm GeO}_{2}/{\rm Al}_{2}{\rm O}_{3}$ </tex-math></inline-formula> Stack

Cited by 9 publications

References 60 publications

Optimization of 7 nm Strained Germanium FinFET Design Parameters Using Taguchi Method and Pareto Analysis of Variance

Optimization of 7 nm Strained Germanium FinFET Design Parameters Using Taguchi Method and Pareto Analysis of Variance

Impact of Channel, Stress-Relaxed Buffer, and S/D Si1−xGe x Stressor on the Performance of 7-nm FinFET CMOS Design with the Implementation of Stress Engineering

Oxygen vacancy defect engineering using atomic layer deposited HfAlOx in multi-layered gate stack

Contact Info

Product

Resources

About