Characterization of SOS-CMOS FETs at Low Temperatures for the Design of Integrated Circuits for Quantum Bit Control and Readout

Ekanayake, Sithumini; Lehmann, Torsten; Dzurak, A. S.; Clark, Robert G.; Brawley, A.

doi:10.1109/ted.2009.2037381

Cited by 76 publications

(39 citation statements)

References 23 publications

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“…"Kink" is significantly larger in NMOS compared to PMOS (see Fig. 2) and reportedly more pronounced in long channel devices for our chosen SOS process [22]. On the other hand, transistors at deep cryogenic temperature still suffer from short channel effects [23].…”

Section: Circuit Operationmentioning

confidence: 80%

Sub-Nanoampere One-Shot Single Electron Transistor Readout Electrometry Below 10 Kelvin

Das

Lehmann

Dzurak

2014

IEEE Trans. Circuits Syst. I

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The Single Electron Transistor holds the potential to be a suitable readout device for future solid-state quantum computers. The low temperature measurement results of a 0.5 Silicon-On-Sapphire CMOS circuit designed to interface with a Single Electron Transistor are presented. Careful design of the experimental set-up is critical for conducting the circuit test and performance measurements at cryogenic temperatures. The circuit operates at 4 K and achieves single-shot readout with a resolution in the order of one nanoampere. A detection delay as low as 1.5 is recorded while dissipating only 20-30 power.

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Section: Circuit Operationmentioning

confidence: 80%

Sub-Nanoampere One-Shot Single Electron Transistor Readout Electrometry Below 10 Kelvin

Das

Lehmann

Dzurak

2014

IEEE Trans. Circuits Syst. I

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“…9). CMOS electronics can be made to work at cryogenic temperatures [152]- [154], and superconducting electronics [155], [156] could serve a naturally complementary role.…”

Section: A Integrationmentioning

confidence: 99%

Silicon Quantum Photonics

Silverstone

Bonneau

O’Brien

et al. 2016

IEEE J. Select. Topics Quantum Electron.

272

194

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Integrated quantum photonic applications, providing physially guaranteed communications security, sub-shot-noise measurement, and tremendous computational power, are nearly within technological reach. Silicon as a technology platform has proven formibable in establishing the micro-electornics revoltution, and it might do so again in the quantum technology revolution. Silicon has has taken photonics by storm, with its promise of scalable manufacture, integration, and compatibility with CMOS microelectronics. These same properties, and a few others, motivate its use for large-scale quantum optics as well. In this article we provide context to the development of quantum optics in silicon. We review the development of the various components which constitute integrated quantum photonic systems, and we identify the challenges which must be faced and their potential solutions for silicon quantum photonics to make quantum technology a reality

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“…However, by relying on the progress of semiconductor technology, only CMOS technology can currently offer the integration of billions of transistors on a single chip, while ensuring low-power consumption, reliability, and functionality down to 30 mK. 113 Beside simple cryogenic CMOS amplifiers, 26,27,114 complex cryogenic analog circuits have been implemented in CMOS, including a full 400 MHz transceiver operating at 173 K 115 and several 4 K analog-to-digital converters (ADC), such as successive approximation register (see Note), 116 Sigma Delta, 117 and Flash ADCs. 76 However, such devices operate at a relatively high temperature (»4 K) or they show poor power efficiency.…”

Section: Scalable Classical Cmos Control Electronics For Fault-toleramentioning

confidence: 99%

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

et al. 2017

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Even the quantum simulation of an apparently simple molecule such as Fe 2 S 2 requires a considerable number of qubits of the order of 10 6 , while more complex molecules such as alanine (C 3 H 7 NO 2 ) require about a hundred times more. In order to assess such a multimillion scale of identical qubits and control lines, the silicon platform seems to be one of the most indicated routes as it naturally provides, together with qubit functionalities, the capability of nanometric, serial, and industrial-quality fabrication. The scaling trend of microelectronic devices predicting that computing power would double every 2 years, known as Moore's law, according to the new slope set after the 32-nm node of 2009, suggests that the technology roadmap will achieve the 3-nm manufacturability limit proposed by Kelly around 2020. Today, circuital quantum information processing architectures are predicted to take advantage from the scalability ensured by silicon technology. However, the maximum amount of quantum information per unit surface that can be stored in silicon-based qubits and the consequent space constraints on qubit operations have never been addressed so far. This represents one of the key parameters toward the implementation of quantum error correction for faulttolerant quantum information processing and its dependence on the features of the technology node. The maximum quantum information per unit surface virtually storable and controllable in the compact exchange-only silicon double quantum dot qubit architecture is expressed as a function of the complementary metal-oxide-semiconductor technology node, so the size scale optimizing both physical qubit operation time and quantum error correction requirements is assessed by reviewing the physical and technological constraints. According to the requirements imposed by the quantum error correction method and the constraints given by the typical strength of the exchange coupling, we determine the workable operation frequency range of a silicon complementary metal-oxide-semiconductor quantum processor to be within 1 and 100 GHz. Such constraint limits the feasibility of fault-tolerant quantum information processing with complementary metal-oxide-semiconductor technology only to the most advanced nodes. The compatibility with classical complementary metal-oxide-semiconductor control circuitry is discussed, focusing on the cryogenic complementary metal-oxide-semiconductor operation required to bring the classical controller as close as possible to the quantum processor and to enable interfacing thousands of qubits on the same chip via timedivision, frequency-division, and space-division multiplexing. The operation time range prospected for cryogenic control electronics is found to be compatible with the operation time expected for qubits. By combining the forecast of the development of scaled technology nodes with operation time and classical circuitry constraints, we derive a maximum quantum information density for logical qubits of 2.8 and 4 Mqb/cm 2 for the 10 and 7-...

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Characterization of SOS-CMOS FETs at Low Temperatures for the Design of Integrated Circuits for Quantum Bit Control and Readout

Cited by 76 publications

References 23 publications

Sub-Nanoampere One-Shot Single Electron Transistor Readout Electrometry Below 10 Kelvin

Sub-Nanoampere One-Shot Single Electron Transistor Readout Electrometry Below 10 Kelvin

Silicon Quantum Photonics

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

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