Charge-based Model for Junction FETs

Abstract

We present a unified charge-based model for double-gate and cylindrical architectures of junction fieldeffect transistors (JFETs). The central concept is to consider the JFET as a junctionless FET (JLFET) with an infinitely thin insulating layer, leading to analytical expressions between charge densities, current, and voltages without any fitting parameters. Assessment of the model with numerical technology computer-aided design simulations confirms that holding the JFET as a special case of the JLFET is justified in all the regions of operation, i.e., from deep depletion to flat-band and from linear to saturation. Index Terms-Cylindrical gate all around junction fieldeffect transistor (JFET), double-gate FETs, nanowire FETs, power semiconductor FETs, radiation-hard electronics, vertical JFET (V-JFET).

SnSe/MoS2 van der Waals Heterostructure Junction Field‐Effect Transistors with Nearly Ideal Subthreshold Slope

“…[11] The SS for JFET has an expression [12] : SS log 10 D gate-to-channel capacitance is much larger than source-to-channel capacitance, the SS of JFET could approach ideal value of ln (10) 60 mVdec 1 kT q = − without sophisticated dielectric engineering, which makes JFETs outperform MOSFET in subthreshold region theoretically. In particular, the absence of dielectric material makes JFET resemble conventional MOSFET with infinite gate capacitance.…”

“…[11] The SS for JFET has an expression [12] : SS log 10 D gate-to-channel capacitance is much larger than source-to-channel capacitance, the SS of JFET could approach ideal value of ln (10) 60 mVdec 1 kT q = − without sophisticated dielectric engineering, which makes JFETs outperform MOSFET in subthreshold region theoretically. [11] Additionally, the dangling bond free van der Waals (vdW) interface formed by 2DSCs could feature a trapping free interface to promise nearly ideal junction characteristics. [18][19][20][21] The 2DSCs is particularly attractive for JFETs since the ultrathin body could reduce source-channel capacitance to minimize the SS and lower the pinch-off voltage V P [22] that is proportional to channel thickness.…”

“…The minimum hysteresis window (≈6 mV) observed in the transfer charactersitics (Figure 2a where Ψ G and Ψ ch is the potential drop in gate and channel, N D and N G is the doping concenteration of channel and gate, [11] respectively. The 2D materials based-JFETs feature dangling-bond free vdW interface, and thus their interface trapping states could be minimized to allow a nearly ideal SS at 60 mV dec −1 at room temperature, as observed in our SnSe/MoS 2 JFET.…”

“…Remarkable shifting of threshold voltage V th is also noticed (Figure 5d). Here, the V th of JEFT is determined by [11] 8 The negative shift of V th of typical MOSFET is normally due to either higher intrinsic carrier concentration or release of electrons from trap state at interface Adv.…”

“…In particular, the absence of dielectric material makes JFET resemble conventional MOSFET with infinite gate capacitance. [11] The SS for JFET has an expression [12] : SS log 10 D Since gate-to-channel capacitance is much larger than source-to-channel capacitance, the SS of JFET could approach ideal value of ln (10) 60 mVdec 1 kT q = − without sophisticated dielectric engineering, which makes JFETs outperform MOSFET in subthreshold region theoretically. [12] Recent studies of 2D materials [13] have revealed a variety of 2D semiconductors (2DSCs) with excellent electronic properties [14][15][16][17] and ultrathin body thickness.…”