Circuit Design For RF Transceivers

Leenaerts, D.M.W.; Tang, J. van der; Vaucher, C.S.

doi:10.1007/b100813

Cited by 78 publications

(44 citation statements)

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“…Actually, the CMOS design at millimeter wave can be characterized by two different approaches which depend on the simulation environments and the related techniques. As an example, analog RF designers prefer to use inductors rather than transmission lines which are used by microwave designers (Leenaerts et al, 2001). Indeed, these choices can have an impact on the layout since transmission lines consume a large area while spiral inductors generally occupy a smaller area .…”

Section: Trends and Challenges In Designing 60 Ghz Building Blocks Inmentioning

confidence: 99%

Trends and Challenges in CMOS Design for Emerging 60 GHz WPAN Applications

Oualkadi¹

2011

Advanced Trends in Wireless Communications

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International audienceThe extensive growth of wireless communications industry is creating a big market opportunity. Wireless operators are currently searching for new solutions which would be implemented into the existing wireless communication networks to provide the broader bandwidth, the better quality and new value-added services. In the last decade, most commercial efforts were focused on the 1-10 GHz spectrum for voice and data applications for mobile phones and portable computers (Niknejad & Hashemi, 2008). Nowadays, the interest is growing in applications that use high rate wireless communications. Multigigabit- per-second communication requires a very large bandwidth. The Ultra-Wide Band (UWB) technology was basically used for this issue. However, this technology has some shortcomings including problems with interference and a limited data rate. Furthermore, the 3-5 GHz spectrum is relatively crowded with many interferers appearing in the WiFi bands (Niknejad & Hashemi, 2008). The use of millimeter wave frequency band is considered the most promising technology for broadband wireless. In 2001, the Federal Communications Commission (FCC) released a set of rules governing the use of spectrum between 57 and 66 GHz (Baldwin, 2007). Hence, a large bandwidth coupled with high allowable transmit power equals high possible data rates. Traditionally the implementation of 60 GHz radio technology required expensive technologies based on III-V compound semiconductors such as InP and GaAs (Smulders et al., 2007). The rapid progress of CMOS technology has enabled its application in millimeter wave applications. Currently, the transistors became small enough, consequently fast enough. As a result, the CMOS technology has become one of the most attractive choices in implementing 60 GHz radio due to its low cost and high level of integration (Doan et al., 2005). Despite the advantages of CMOS technology, the design of 60 GHz CMOS transceiver exhibits several challenges and difficulties that the designers must overcome. This chapter aims to explore the potential of the 60 GHz band in the use for emergent generation multi-gigabit wireless applications. The chapter presents a quick overview of the state-of-the-art of 60 GHz radio technology and its potentials to provide for high data rate and short range wireless communications. The chapter is organized as follows. Section 2 presents an overview about 60 GHz band. The advantages are presented to highlight the performance characteristics of this band. The opportunities of the physical layer of the IEEE 802.15.3c standard for emerging WPAN applications are discussed in section 3. The tremendous opportunities available with CMOS technology in the design of 60 GHz radio is discussed in section 4. Section 5 shows an example of 60 GHz radio system link. Some challenges and trade-offs on the design issues of circuits and systems for 60 GHz band are reported in section 6. Finally, section 7 presents the conclusion and some perspectives on future directions

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Section: Trends and Challenges In Designing 60 Ghz Building Blocks Inmentioning

confidence: 99%

Trends and Challenges in CMOS Design for Emerging 60 GHz WPAN Applications

Oualkadi¹

2011

Advanced Trends in Wireless Communications

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“…2) [9] has been synthesized. The most important feature of the cascode transistor is that a common-gate stage results in a higher power gain compared to a single stage.…”

Section: Lna Systematic Design and Characterizationmentioning

confidence: 99%

“…Note that to be matched, the real part of the input impedance must be equal to the source resistance R s . To obtain a real impedance at the input, the capacitive part of impedance should be compensated with inductances [9]. As mentioned above, these decisions are made based on the approximative expression of input impedance.…”

Section: Choice Of Inductorsmentioning

confidence: 99%

LNA automatic synthesis and characterization for accurate RF system-level simulation

Haghighitalab¹,

Vasilevski²,

Aboushady³

2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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Abstract-In this paper, we propose an automatic design procedure for the synthesis of a cascode LNA with inductive source degeneration. The proposed method is based on the precise characterization of noise figure, input impedance and gain. The design procedure is implemented in a C++ environment using a BSIM3v3-based tool for transistor sizing and a symbolic computation tool for circuit characterization. SystemC AMS can then be used to perform a system level simulation of a complete RF receiver using precise model of the LNA. Considering the complete equivalent model for the transistors and the inductors, two LNAs operating at 2.4 GHz and 935 MHz are synthesized and characterized for a 130 nm CMOS process. The generated accurate model is then used in a high-level simulation of a complete QPSK-based RF receiver to study the effect of the LNA noise figure on the Bit Error Rate of the receiver.

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“…The control modulus signal is set to "low", the prescaler divides by N. The main counter continues down counting with input clock Fout/N until it reaches zero. After the two counters are reset, the process begins again [9,10] . The output frequency Fdiv can be expressed as a function of the input frequency Fout as follows: When the Mode signal is low, the NAND output "A" is high and M2 is turned ON.…”

Section: Integer-n Programmable Dividermentioning

confidence: 99%

Low Power Phase Locked Loop Frequency Synthesizer for 2.4 GHz Band Zigbee

Ismail¹,

Othman²

2009

American J. of Engineering and Applied Sciences

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Problem statement: Wireless communication systems are required for many applications. There are different standards for these systems. IEEE 802.15.4 defines the communication system standard for Zigbee. This study discussed designing one of the blocks of Zigbee transceiver which is the Phase Locked Loop (PLL). A major target for any communication systems is saving battery power, especially for Zigbee as it is meant to be a low cost communication system. Phase locked loop is responsible on carrier frequency selection in a communication system. It is the most power consumer block in the transceiver as well. The objective of this study was designing a low power fully integrated integer-N PLL frequency synthesizer targeting the 2.4 GHz band IEEE 802.15.4 Std Zigbee. Approach: Minimizing total power consumption of PLL was achieved by introducing a novel design of Phase Frequency Detector (PFD) and modifying the rest of the PLL blocks. The proposed PFD used only 12 transistors and it preserved the main characteristics of the conventional PFD with a simple architecture. The Charge Pump (CP) was single-ended source switch to save power and minimize mismatches. The Voltage Controlled Oscillator (VCO) spans from 4.737-4.977 GHz band using LC resonator. The VCO worked at double the frequency band to avoid local oscillator leakage and feed through. The integer N divider used a 15/16 dual modulus. Results: The proposed PLL was designed using Silterra 0.18 um CMOS process. It consumed 3.2 mW with 1.8 voltage supply. Phase noise is-113.4 dBc Hz −1 at 1 MHz. The proposed PFD works up to 2.5 GHz with free dead zone. The Charge Pump (CP) works with 20 uA, lock-in time is 27 us and total die area is 1×2 mm. All results were taken from extracted layout simulations. Conclusion: The results of this study indicated that a PLL can work with less power consumption and save the transceiver battery. The proposed PFD was suitable for high speed applications.

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Circuit Design For RF Transceivers

Cited by 78 publications

References 0 publications

Trends and Challenges in CMOS Design for Emerging 60 GHz WPAN Applications

Trends and Challenges in CMOS Design for Emerging 60 GHz WPAN Applications

LNA automatic synthesis and characterization for accurate RF system-level simulation

Low Power Phase Locked Loop Frequency Synthesizer for 2.4 GHz Band Zigbee

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