Clock rate versus IPC

Abstract

The doubling of microprocessor performance every three years has been the result of two factors: more transistors per chip and superlinear scaling of the processor clock with technology generation. Our results show that, due to both diminishing improvements in clock rates and poor wire scaling as semiconductor devices shrink, the achievable performance growth of conventional microarchitectures will slow substantially. In this paper, we describe technology-driven models for wire capacitance, wire delay, and microarchitectural component delay. Using the results of these models, we measure the simulated performance-estimating both clock rate and IPCof an aggressive out-of-order microarchitecture as it is scaled from a 250nm technology to a 35nm technology. We perform this analysis for three clock scaling targets and two microarchitecture scaling strategies: pipeline scaling and capacity scaling. We find that no scaling strategy permits annual performance improvements of better than 12.5%, which is far worse than the annual 50-60% to which we have grown accustomed.

A scalable micro wireless interconnect structure for CMPs

“…In recent years, the performance increases possible with conventional superscalar single-core processors have encountered fundamental limits [1,5], leading to an industry-wide turn towards chip multiprocessor (CMP) systems.…”

“…Our hybrid architecture employs virtual channels (VCs) [12], where each physical channel is split into several VCs (rather than a single FIFO buffer). 1 In order to break deadlock in the hybrid architecture, we define two types of VCs per physical channel, * Up and * Down. Only the physical channels between base routers have both types of VCs, and other physical channels (e.g., between a wireless router and a base router) have only * Down channels.…”

“…CMP's have been widely acclaimed as the architecture of choice for future high-performance processors [1,28]. Today's CMPs support tens to low hundreds of cores, including Intel's 80-core Terascale chip [32] and NVIDIA's 128-core Quadro GPU [26].…”

Heterogeneous Clustered VLIW Microarchitectures

“…They do not propose novel approaches to perform distribution of the instructions among clusters. Instead, our poprosal targets both problems by: (1) proposing a novel method to perform off-line reconfiguration of the microarchitecture at the program level, and (2) proposing a new scheme for instruction distribution to produce improvements in ED2.…”

“…The components of each cluster are simpler, faster, and consume less power. The resources in a cluster can be laid out in close proximity, which reduces signal transmission delays [1]. Long (and slow) wires are used to interconnect clusters.…”