CMOS flash analog-to-digital converter for high speed and low voltage applications

Yoo, Jincheol; Choi, Kyusun; Ghaznavi, Jahan

doi:10.1145/764808.764823

Cited by 11 publications

(5 citation statements)

References 4 publications

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“…We propose high speed CNFET Flash ADC architecture with low power consumption, which is featuring the threshold inverter quantization (TIQ) comparator technique [25,26]. The comparators are the most critical components in a flash ADC.…”

Section: Fig 3 Block Diagram Of the Tiq Adc Tiq Comparatormentioning

confidence: 99%

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

Sankar

Sathiyabama

2015

JERA

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The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

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Section: Fig 3 Block Diagram Of the Tiq Adc Tiq Comparatormentioning

confidence: 99%

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

Sankar

Sathiyabama

2015

JERA

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“…The switched inverter scheme (SIS) also called Threshold inverter quantization (TIQ) comparator has very simple architecture as shown in Fig.3 [37], [38]. It is quite different than the conventional operational amplifier based differential input voltage (DIV) comparator [9], [28], [34]. The key difference between the DIV comparator and the (SIS) comparator scheme lies in the way the reference voltage is generated for each level.…”

Section: Switched Inverter Scheme (Sis) Comparatormentioning

confidence: 99%

“…Out of various ADC architectures available, the design of flash ADC becomes quite more important as it is used in other ADC architectures like two step ADC and multi bit sigma delta ADC. The block diagram of a flash ADC is as shown in Fig.2 [26], [34].…”

Section: Introductionmentioning

confidence: 99%

Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter

Sunaniya¹,

Khare

2013

VLSICS

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This work presents three different approaches which eliminates the resistor ladder completely and hencereduce the power demand drastically of a Analog to Digital Converter. The first approach is SwitchedInverter Scheme (SIS) ADC; The test result obtained for it on 45nm technology indicates an offset error of0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;Power delay product (PDP) is 415.9 fWs, and the area is 1.89μm2. The second and third approaches areclocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in powerdissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SISADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC

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“…As a result, there is a trade-off between the area and the quality of the resolution [2]. A parallel link of 2 N -1 comparators is needed to design an N-bit FADC [3] with high-resolution quality. It takes an analogue voltage signal (V in ) as input and compares it to V ref using comparators.…”

Section: Introductionmentioning

confidence: 99%

Design and Analysis of 4-bit 1.2GS/s Low Power CMOS Clocked Flash ADC

Prathiba¹,

Santhi²

2022

Intelligent Automation &Amp; Soft Computing

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High-quality, high-resolution flash ADCs are used in reliable VLSI (Very Large-Scale Integrated) circuits to minimize the power consumption. An analogue electrical signal is converted into a discrete-valued sequence by these ADCs. This paper proposes a four-bit 1.2GS/s low-power Clocked Flash ADC (C-FADC). A low-power Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble Free (ABF) logic circuit, and a compact Binary Encoder (BE) are all part of the presented structure. A clock network in the comparator circuit reduces skew and jitters, while an ABF logic circuit detects and corrects fourth order bubble faults detected from thermometer code, and then the BE transforms the bubble free code into binary code. A Tanner EDA with 250-nm Technology is used to implement the C-FADC. The proposed design achieves ENOB of 3.56, uses 3.24 mW of power, and has a FOM of 0.274pJ/conv.-step at an input frequency of 85 MHz. The suggested C-FADC has differential and integral nonlinearities of ±0.65 LSB and +0.45/-0.5 LSB, respectively.

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CMOS flash analog-to-digital converter for high speed and low voltage applications

Cited by 11 publications

References 4 publications

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter

Design and Analysis of 4-bit 1.2GS/s Low Power CMOS Clocked Flash ADC

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