CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Abstract

Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wetcompatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

A Platform for Complementary Metal‐Oxide‐Semiconductor Compatible Plasmonics: High Plasmonic Quality Titanium Nitride Thin Films on Si (001) with a MgO Interlayer

“…[14] TiN has been widely used as a gate electrode in various CMOS devices. [15][16][17][18] In the area of plasmonics, TiN-based waveguides, [19] gyroidal metamaterials, [20] nanohole metasurfaces, [21] nanoantennas, [22][23][24] and use of TiN nanoparticles for solar energy conversion [25,26] and biomedicine [27] have been reported.However, the majority of the demonstrations of TiN's device potential in plasmonics have been on sapphire and bulk MgO substrates featured by their small lattice mismatch with TiN, enabling the best-performing plasmonic films. [24,[28][29][30][31][32][33] Even then, high deposition temperatures (not congruent with CMOS processes) were usually used to ensure the high structural quality of the TiN films.…”

“…[14] TiN has been widely used as a gate electrode in various CMOS devices. [15][16][17][18] In the area of plasmonics, TiN-based waveguides, [19] gyroidal metamaterials, [20] nanohole metasurfaces, [21] nanoantennas, [22][23][24] and use of TiN nanoparticles for solar energy conversion [25,26] and biomedicine [27] have been reported.…”

Challenges and Solutions of Replacement Metal Gate Patterning to Enable Gate-all-Around Device Scaling

“…The typical dipole patterning is so called dipole last scheme, where the dipole element, e.g. lanthanum, is deposited on high-k dielectrics and subsequently it is driven into the interface of high-k and interlayer (IL) by an annealing [10]. However, the dipole last patterning would be difficult to apply to the nanosheet devices because of the confined nanosheet spacing.…”

(Invited) Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges

“…Since it can modulate the effective WF without increasing physical thickness, it could be a promising solution for the Vt tuning of the GAA devices, which will have aggressively scaled Lg, fin pitches as well as vertical nanowire and nanosheet pitches. The patterning scheme could be so called diffusion and gate replacement (D&GR), where the dipole elements will be driven into the HK/IL interface (27,28). However, the mechanism of dipole formation is not fully understood yet.…”