CMOS SRAM functional test with quiescent write supply current

Hashizume, Masaki; Tamesada, Takeomi; Koyama, Takeshi; Goor, A.J. van de

doi:10.1109/iddq.1998.730724

Cited by 4 publications

(8 citation statements)

References 6 publications

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“…IDDQ testing can detect some of the open defects in SRAM too e.g. opens in word line (WR) or in bit line (BL) (marked as A and B in figure 4), which can be modeled as data retention fault (DRF) [3]. Open defects in the drain (source) of transistors and floating gate defects behaving as stuck-open transistors are also detected by IDDQ testing [9].…”

Section: Iddq Testing For Drg-cachementioning

confidence: 99%

“…Hashizume et al [3] examined if faulty CMOS SRAM ICs, which cannot produce the expected outputs, can be detected by measuring quiescent power supply current generated during write operation. They demonstrated that write cycle supply current is in the range of mA, which can be easily measured by test equipment.…”

Section: Previous Work On Iddq Testing In Srammentioning

confidence: 99%

“…Since the quiescent current for a "good" CMOS circuit is very small, if an abnormally high IDDQ is detected for the DUT, it is determined to be faulty. Test techniques that monitor the IDDQ of CMOS circuits are effective to detect defects causing significant change in leakage [3,4,9,10,14]. For CMOS SRAM circuits, the defects which can be detected by IDDQ testing include most of the bridging defects which can be modeled as stuck-at fault (SAF) e.g.…”

Section: Iddq Testing For Drg-cachementioning

confidence: 99%

“…IDDQ testing is based on determining the quiescent supply current and can be used for burn-in elimination and for identifying issues related to yield and reliability [6,14,15]. Many defects, which do not generate any effect on output values of a memory cell and hence, cannot be modeled as functional faults, may be detected by IDDQ testing [3,7]. Hence, few IDDQ vectors can be used effectively in memories to weed out some latent or reliability defects before applying functional testing [6,7].…”

Section: Introductionmentioning

confidence: 99%

“…IDDQ testing has been established as an effective technique [3,4,6,7,9,10] to test CMOS SRAMs for realizing highly reliable systems. IDDQ testing is based on determining the quiescent supply current and can be used for burn-in elimination and for identifying issues related to yield and reliability [6,14,15].…”

Section: Introductionmentioning

confidence: 99%

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A high performance IDDQ testable cache for scaled CMOS technologies

Bhunia

Roy

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

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Quiescent supply current (IDDQ) testing is a useful test method for static CMOS RAM and can be combined with functional testing to reduce total test time and to increase reliability. However the sensitivity of IDDQ testing deteriorates significantly with technology scaling as intrinsic leakage of CMOS circuits increases. In this paper, we use a design technique for high-performance cache, which greatly improves leakage current and hence the IDDQ testability of the cache with technology scaling. We utilize the concept of Gated-Ground [1, 2] (NMOS transistor inserted between ground line and SRAM cell) to achieve reduction in leakage energy due to stacking effect of transistor without significantly affecting performance. Simulation results for a 64K cache shows 20% average improvement in IDDQ sensitivity for TSMC 0.25µm technology, while the improvement is more than 1000% for 70nm predictive technology model [12].

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Section: Iddq Testing For Drg-cachementioning

confidence: 99%

Section: Previous Work On Iddq Testing In Srammentioning

confidence: 99%

Section: Iddq Testing For Drg-cachementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A high performance IDDQ testable cache for scaled CMOS technologies

Bhunia

Roy

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

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Equivalent IDDQ Tests for Systems with Regulated Power Supply

Chen

Xia

2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Hard-to-Detect Fault Analysis in FinFET SRAMs

Medeiros

Fieback

et al. 2021

IEEE Trans. VLSI Syst.

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Manufacturing defects can cause Hard-to-Detect (HTD) faults in FinFET SRAMs. Detection of these faults, such as random read outputs and out-of-spec parametric deviations, is essential when testing FinFET SRAMs. Undetected HTD faults result in test escapes, which lead to early in-field failures. This paper presents a detailed analysis of HTD faults in FinFET SRAMs by exploring their sensitization and discussing solutions to improve HTD fault coverage during manufacturing testing. We first define the fault space for SRAMs and classify all faults in the space. Following this, we perform a systematic fault analysis based on injecting resistive defects in a memory cell, inspecting its behavior, and identifying HTD faults. Furthermore, we survey existing test solutions and discuss their HTD fault coverage and limitations. Based on our analysis, it is clear that no single test solution can fully detect all HTD faults, thus leading to test escapes. Hence, there is a need for new and more efficient test solutions. Improved detection of HTD faults could be achieved by using parametric test solutions, proposing solutions that cover yet-untargeted HTD faults, combining multiple test approaches into a single solution, and further exploring stress conditions. These new approaches would reduce test escapes and therefore improve the quality of FinFET SRAMs.

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CMOS SRAM functional test with quiescent write supply current

Cited by 4 publications

References 6 publications

A high performance IDDQ testable cache for scaled CMOS technologies

A high performance IDDQ testable cache for scaled CMOS technologies

Equivalent IDDQ Tests for Systems with Regulated Power Supply

Hard-to-Detect Fault Analysis in FinFET SRAMs

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