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A new high speed IDDQ test method is proposed. It is based on charge current for load capacitances of gates whose output logic values are changed from L to H by test input vector application. In this paper, the testability of the test method is examined for some process variations generated in CMOS IC production.

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In this paper, test input vectors for ISCAS-85 benchmark circuits are derived, with which single faults of each signal line in the lTL combinational circuits can be detected by their quiescent supply currents. Also, they are compared with the vectors for fault detection methods based on the primary output logic values. It is shown that by detecting faults with supply currents of T7z circuits, smaller size of test inputs can be derived for most of the circuits than fault detection methods based on the primary output logic values, and ako, if both the output logic values and the supply current are used for detecting faults, the number of the test inputs can be reduced.

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