CMOS switched current phase-locked loop

Abstract

Abstract:The authors present an integrated circuit realisation of a switched current phaselocked loop (PLL) in standard 2 . 4~ CMOS technology. The centre frequency is tunable to IFdHz at a clock frequency of 5.46MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes < 2mW from a 3.3V power supply.