3]) there are no stability issues and settling can be fast. Due to B. Putter the 2-phase switching, the 1st aliasing components originate from the band around twice the clock frequency. Aliasing, however, NXP Semiconductors, Zurich, Switzerland also occurs from the band around the clock frequency, this due to the finite transconductance of the opamp in the lst integrator and With the advent of new cellular communication standards like the time-varying output impedance of the SC DAC. UMTS and the large install-base of current standards like GSM, mobile devices capable of working in different modes are desir-The comparator shown in Fig. 13.4.4 is designed for high bandable. In order to support multiple modes, a reconfigurable receive width, fast settling, and rail-to-rail output signals. When the chain is the preferred option to minimise total silicon area. clock signal is low, the input signal (a differential current) gener-Because of the potential for low power consumption and inherent ates a differential voltage on the sources of transistors MNo and anti-aliasing behaviour [1], a CT AL ADC is often preferred for MN1 (charge difference on Cgs of the transistors). When the clock

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Abstract:The authors present an integrated circuit realisation of a switched current phaselocked loop (PLL) in standard 2 . 4~ CMOS technology. The centre frequency is tunable to IFdHz at a clock frequency of 5.46MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes < 2mW from a 3.3V power supply.