Abstract-In this paper, we present a new type of switched current memory cell with a three phase clock cycle. The design technique is based on differential error matching, which leads to input currents between 50 and 85 PA. The conversion period is 700 ns, which is significantly lower, compared to other results presented in the literature, taking into account the error. Still higher speeds can be obtained by using shorter channel-length technologies.a high accuracy cell with measured errors less than 200 ppm for s, is:7 SI

Abstract:The authors present an integrated circuit realisation of a switched current phaselocked loop (PLL) in standard 2 . 4~ CMOS technology. The centre frequency is tunable to IFdHz at a clock frequency of 5.46MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes < 2mW from a 3.3V power supply.

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Abstract-In this paper, we present a new type of switched current memory cell with a three phase clock cycle. The design technique is based on differential error matching, which leads to input currents between 50 and 85 PA. The conversion period is 700 ns, which is significantly lower, compared to other results presented in the literature, taking into account the error. Still higher speeds can be obtained by using shorter channel-length technologies.a high accuracy cell with measured errors less than 200 ppm for s, is:7 SI