A high-performance SI memory cell

Abstract

Abstract-In this paper, we present a new type of switched current memory cell with a three phase clock cycle. The design technique is based on differential error matching, which leads to input currents between 50 and 85 PA. The conversion period is 700 ns, which is significantly lower, compared to other results presented in the literature, taking into account the error. Still higher speeds can be obtained by using shorter channel-length technologies.a high accuracy cell with measured errors less than 200 ppm for s, is:7 SI

A 3.3 V 625 kHz switched-current multiplier

“…A central element in SI circuits is the memory cell [l], [2] allowing for short-term storage of currents. The SI technique is often applied in filters, but its application area is rapidly growing [3] and comprises oscillators, digital-to-analog converters (DAC' s), algorithmic analog-to-digital converters (ADC's), Sigma-Delta converters, cellular neural networks, etc.…”

A MATLAB Model of the Second Generation Switched Current Memory Cell

“…There is regulated cascode used to increase output impedance of the memory transistor [3]. Simple parallel combination of the NMOS and PMOS transistors is used as a switch [4]. The injected charge of the switch leads to change of memory transistor gate voltage and also to change of the memorized current.…”

A four-quadrant S/sup 2/I switched-current multiplier

“…This paper presents an alternative implementation by using the S I switched-current technique that has already been proven effective in filtering and converting applications [12]- [14]. One of the most important features of S I is that it allows to compensate for analog errors due to charge injection [10], [14], [15] as well as for those arising from the finite output impedance. The signal-dependent clock feedthrough is sampled and stored in the initial sampling phase of the current copier operation and then algebraically added to the corrupted current to minimize the corresponding error.…”