Coding efficiency optimization for multilevel PWM based switched-mode RF transmitters

Chi, Shuli; Singerl, Peter; Vogel, Christian

doi:10.1109/mwscas.2011.6026539

Cited by 20 publications

(16 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…By doing so the drain efficiency of the PA is high, but power is lost as the resulting modulation sidebands from the PWM are dissipated in an isolator, which results in a Class-B efficiency curve for a single level PA. But when using a multilevel PA structure such as the switchable cascode presented in this paper a Doherty like efficiency curve can be achieved [1]. In trace 'BB PWM' shown in Fig.…”

Section: Bb Pwm and Direct Filter Connectionmentioning

confidence: 85%

“…2, the resulting power added efficiency is given in trace PAE 1 . The power added efficiency in this case was calculated according to (1) and is 65.4 %. The corresponding gain g 1 is also shown, where trace g 2 depicts the gain for normal PA operation.…”

Section: Circuit Implementationmentioning

confidence: 99%

“…To improve the efficiency several efficiency enhancement methods such as baseband PWM (BB PWM) [1] have been developed. Unfortunately BB PWM does only result in a Class-B efficiency curve for a single level PA.…”

Section: Introductionmentioning

confidence: 99%

“…Unfortunately BB PWM does only result in a Class-B efficiency curve for a single level PA. In order to achieve efficiency improvement multilevel PA structures are required [1]. In addition to BB PWM the concept of direct filter connection, which uses a series resonator to provide high impedance for the modulation sidebands, can be employed to further boost the efficiency.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

An integrated switchable cascode RF power amplifier in GaN technology

Seebacher

Bösch

Singerl

et al. 2013

IEEE MTT-S International Microwave and RF Conference

Self Cite

View full text Add to dashboard Cite

In this paper an integrated switchable cascode RF power amplifier (PA) will be presented. Modern communication standards use coding schemes with high peak to average power ratios (PAPR) therefore PA efficiency in back off is key to efficient transmitters. The proposed switchable cascode PA, which is based on a modified cascode structure, is capable of providing such an efficiency peak in back off. The operational principle is explained and a possible circuit implementation in GaN technology at 2.65 GHz is presented. At a maximum power of 2.74 W the circuit has a power added efficiency (PAE) of 65.4 % and at 0.57 W (6.7 dB backoff) a PAE of 60.2 %. In addition the combination with other efficiency enhancement methods such as baseband PWM or direct filter connection are covered.

show abstract

Section: Bb Pwm and Direct Filter Connectionmentioning

confidence: 85%

Section: Circuit Implementationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

An integrated switchable cascode RF power amplifier in GaN technology

Seebacher

Bösch

Singerl

et al. 2013

IEEE MTT-S International Microwave and RF Conference

Self Cite

View full text Add to dashboard Cite

show abstract

“…8-PSK or /4-DQPSK) with required values of the dynamic range in excess of 10 dB. One approach which can be used to enhance the dynamic range is to combine the output power of several transmit chains [5], [7], [8]. The individual transmit chains are excited by dedicated PWMD chips whose duty cycle range can be controlled individually, as in Fig.…”

Section: B Dynamic Range and Bandwidthmentioning

confidence: 99%

A 250 nm CMOS / LDMOS Pulse-Width Modulator and Driver for space-borne GaN switch mode power amplifiers in P-Band

Ghosh

Altmann

Kersten

et al. 2014

2014 44th European Microwave Conference

View full text Add to dashboard Cite

In this paper, the design of a single-chip RF PulseWidth Modulator and Driver (PWMD) aimed at exciting a 80 W class-E GaN high-power stage at 435 MHz is described. For the required buffer size, avoiding potential ringing of the pulses within the buffer structure presents a major challenge in the design process. Therefore, a smaller chip capable of driving capacitive loads of up to 5 pF was initially designed, fabricated and tested. An approach based on 3D EM simulations was used to validate the test results. Based on the presented results, an enlarged chip able to drive a 80 W GaN high-power stage is currently being designed.

show abstract