We present an integrated fractional-N lownoise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is -87 dBc/Hz and -106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to -98 dBc/Hz at 10 kHz and -111 dBc/Hz at 1 MHz offset, respectively, were measured.

In this paper, the design of a single-chip RF PulseWidth Modulator and Driver (PWMD) aimed at exciting a 80 W class-E GaN high-power stage at 435 MHz is described. For the required buffer size, avoiding potential ringing of the pulses within the buffer structure presents a major challenge in the design process. Therefore, a smaller chip capable of driving capacitive loads of up to 5 pF was initially designed, fabricated and tested. An approach based on 3D EM simulations was used to validate the test results. Based on the presented results, an enlarged chip able to drive a 80 W GaN high-power stage is currently being designed.

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In this paper, we present design, implementation and measurement of 3-D mm-wave LTCC (Low Temperature Cofired Ceramic) module with vertical transition through FR-4 PCB substrate. A new structure in order to transfer mm-wave signal from transceiver module through an opening in FR-4 PCB substrate to antenna with standard WR-22 waveguide port is proposed. The module features front-end, receiver and transmitter. The opening in FR-4 PCB substrate is of rectangular type, which has the same dimensions as a WR-22 waveguide. The edge of the opening is conductively plated with copper from top side to the bottom to reduce transmission losses. The implemented module is compact in size (32 x 28 x 3.3 mm 3 ). Experimental results show a 1dB compression output power of 15dBm and noise figure of 9.72dB at 40.5~41.5GHz.

In this paper, the design of a single-chip RF Pulse-Width Modulator and Driver (PWMD) aimed at exciting a 80 W class-E GaN high-power stage at 435 MHz is described. For the required buffer size, avoiding potential ringing of the pulses within the buffer structure presents a major challenge in the design process. Therefore, a smaller chip capable of driving capacitive loads of up to 5 pF was initially designed, fabricated and tested. An approach based on 3D EM simulations was used to validate the test results. Based on the presented results, an enlarged chip able to drive a 80 W GaN high-power stage is currently being designed.