Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor

Sarkhel, Saheli; Bagga, Navjeet; Sarkar, Subir Kumar

doi:10.1007/s10825-015-0772-3

Cited by 32 publications

(5 citation statements)

References 32 publications

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“…These models are highly desirable because they offer better computational efficiency than their numerical alternatives without loss of physical insights. Since T. Kacprzak et al had reported firstly the compact DC model of GaAs-FETs in 1983 [28], the compact model for FETs has received much attention [29][30][31][32][33]. Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Since Kacprzak et al reported firstly the compact DC model of GaAs-FETs in 1983, [28] the compact model for FETs has received much attention. [29][30][31][32][33] [34,35] which is based on the charge sheet model of MOSFET. Following Meric's model, several evolving compact models have been established, [36][37][38][39] such as, virtual-source current-voltage model, SPICE-compatible compact model, and electrical compact model, etc.…”

Section: Introductionmentioning

confidence: 99%

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A review for compact model of graphene field-effect transistors

Wang

et al. 2017

Chinese Phys. B

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Graphene has attracted enormous interests due to its unique physical, mechanical, and electrical properties. Specially, graphene-based field-effect transistors (FETs) have evolved rapidly and are now considered as an option for conventional silicon devices. As a critical step in the design cycle of modern IC products, compact model refers to the development of models for integrated semiconductor devices for use in circuit simulations. The purpose of this review is to provide a theoretical description of current compact model of graphene field-effect transistors. Special attention is devoted to the charge sheet model, drift-diffusion model, Boltzmann equation, density of states (DOS), and surface-potential-based compact model. Finally, an outlook of this field is briefly discussed.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A review for compact model of graphene field-effect transistors

Wang

et al. 2017

Chinese Phys. B

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“…In many literature numerous structures and ideas have been reported to suppress the ambipolarity which includes gate-drain underlap [16] and gate-drain overlap [17,18] techniques but that causes a profound impact on the gate-drain capacitance and ON current level. The work function engineered dual metal, triple metal and linearly graded tunnel FETs [14], [19,20] reduces the ambipolarity but at the cost of an increase in Miller capacitance which affects the high-frequency parameters. Moreover, the heterodielectric TFETs [21] are also reported to suppress the ambipolar current.…”

Section: Introductionmentioning

confidence: 99%

Demonstration of a novel tunnel FET with channel sandwiched by drain

Bagga

Chauhan

Banchhor

et al. 2019

Semicond. Sci. Technol.

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A novel double gate tunnel FET with channel sandwiched by drain (CSD-TFET) is proposed and investigated in this paper. The proposed CSD-TFET consists of three differently doped drain layers in which the middle layer is an extension of the channel and is sandwiched by the heavily doped top and bottom drain layers. The objective of the proposed endeavor is to reduce the ambipolar current without affecting the ON current. We have compared the results of CSD-TFET with the reference tunnel FET (RTFET) designed by using the same simulation setup as opted for simulating the proposed CSD-TFET. The extracted ambipolar current of CSD-TFET is ∼10 4 times lower than that of RTEFT with no change in the ON current. An interesting flipping/ crossover phenomenon in the gate-to-drain capacitance (C gd ) of the proposed CSD-TFET at a certain gate-to-drain voltage (V GD ) is observed. We also discussed the saturation phenomenon of the drain current and the variation of unity gain frequency with C gd .

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“…The primary constrains concerning TFET devices are ambipolar conduction [13, 14], which originates from the BTBT at the drain–channel junction and other is low ON current, which are considerably poorer than MOSFETs. Various improvements have been investigated to compensate for these limitations faced by TFETs [15, 16].…”

Section: Introductionmentioning

confidence: 99%

Analytical modelling and simulation of drain doping engineered splitted drain structured TFET and its improved performance in subduing ambipolar effect

Bhattacharjee

Goswami

Dash

et al. 2019

IET Circuits, Devices & Systems

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The study presents an analytical model for the potential distribution of a drain doping engineered 2D tunnelling field effect transistor (TFET) with splitted drain structure. Hence, tunnelling drain current is derived using this potential distribution. Further, the study analyses the influence of drain doping engineering on all characteristics and parameters of a TFET model. Splitted drain structure exhibits major reduction in ambipolar conduction due to increase of the tunnelling width at the channeldrain junction. Simulation of four different structures of the device consisting of splitted drain region with relative location and doping concentration is executed. The structures are named according to the relative position of the drain: splitted-drain singlegate TFET (SD-SG TFET: total drain is splitted), top-splitted-drain single-gate TFET (TSD-SG TFET: splitted-drain in upper location), Mesial-splitted-drain single-gate TFET (MSD-SG TFET: splitted-drain in middle location), and basal-splitted-drain single-gate TFET (BSD-SG TFET: splitted-drain in bottom location). All the fundamental device characteristics and parameters are analysed for all the four structures, and their merits and drawback are recorded for optimal valuation and detection of better structure. All the proposed structures show improved performance with suppressed gate leakage and ambipolarity than conventional planar TFET. All the simulations are done in Silvaco, Atlas.

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Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor

Cited by 32 publications

References 32 publications

A review for compact model of graphene field-effect transistors

A review for compact model of graphene field-effect transistors

Demonstration of a novel tunnel FET with channel sandwiched by drain

Analytical modelling and simulation of drain doping engineered splitted drain structured TFET and its improved performance in subduing ambipolar effect

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