Compact Modeling of Perpendicular STT-MTJs With Double Reference Layers

Rose, Raffaele De; d’Aquino, M.; Finocchio, G.; Crupi, Felice; Carpentieri, Mario; Lanuzza, Marco

doi:10.1109/tnano.2019.2945408

Cited by 30 publications

(36 citation statements)

References 31 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As shown in Figure 1c, a perpendicular magnetic anisotropy (PMA) DMTJ device consists of three stacked ferromagnetic (FM) layers separated by two MgO barriers with different thickness (t OX,T and t OX,B ). The top and bottom FM layers, namely reference layer top (RL T ) and reference layer bottom (RL B ), have a fixed magnetization orientation opposite to each other [29]. The remaining FM layer, known as free layer (FL), has a variable magnetization orientation, i.e., parallel (P) or antiparallel (AP) with respect to that of the RL T or RL B layer.…”

Section: Double-barrier Magnetic Tunnel Junction (Dmtj)mentioning

confidence: 99%

“…In particular, our study was carried out at the memory-bitcell level in which TFET-based DMTJ STT-MRAM bitcells have been benchmarked against their FinFET-based counterparts. Our analysis exploits a state-of-the-art DMTJ Verilog-A compact model [29]. For the simulation of transistors, we used a complementary TFET technology [30] and a predictive technology model (PTM) of 10 nm node FinFET [14], both operating in the sub-threshold voltage regime.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

et al. 2021

Self Cite

View full text Add to dashboard Cite

Spin-transfer torque magnetic tunnel junction (STT-MTJ) based on double-barrier magnetic tunnel junction (DMTJ) has shown promising characteristics to define low-power non-volatile memories. This, along with the combination of tunnel FET (TFET) technology, could enable the design of ultralow-power/ultralow-energy STT magnetic RAMs (STT-MRAMs) for future Internet of Things (IoT) applications. This paper presents the comparison between FinFET- and TFET-based STT-MRAM bitcells operating at ultralow voltages. Our study is performed at the bitcell level by considering a DMTJ with two reference layers and exploiting either FinFET or TFET devices as cell selectors. Although ultralow-voltage operation occurs at the expense of reduced reading voltage sensing margins, simulations results show that TFET-based solutions are more resilient to process variations and can operate at ultralow voltages (<0.5 V), while showing energy savings of 50% and faster write switching of 60%.

show abstract

Section: Double-barrier Magnetic Tunnel Junction (Dmtj)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

et al. 2021

Self Cite

View full text Add to dashboard Cite

show abstract

“…based Verilog-A compact model [10], which also mimics the 3. Circuit-and architecture-level analysis at 77 K A summary of the bitcell-level MC results is provided in write latency of more than 70% in comparison to its 40 nm…”

Section: Device-level Modelingmentioning

confidence: 99%

Relaxing non-volatility for energy-efficient DMTJ based cryogenic STT-MRAM

Garzón

Rose

Crupi

et al. 2021

Solid-State Electronics

Self Cite

View full text Add to dashboard Cite

Spin-transfer torque magnetic random-access memory (STT-MRAM) is considered a potential universal memory that could replace conventional six-transistors static random-access memory (6T-SRAM) in processor caches. This paper explores STT-MRAMs based on double-barrier magnetic tunnel junction (DMTJ), while operating at cryogenic temperatures (77 K). To deal with large dynamic energy and long write latency of magnetic memories we suggest to significantly relax the non-volatility requirement (i.e., by reducing cross-section area) of the DMTJ devices at room temperature, while maintaining the typical ten year storage retention time at the target operating temperature. This leads the DMTJ-based STT-MRAM to be more energy-efficient under both read/write operations than 6T-SRAM, while maintaining a smaller area footprint.

show abstract

“…In this paper, we present a comparative evaluation between GC-eDRAM, 6T-SRAM, and STT-MRAM memories when operating at 77 K. The analysis is carried out based on a 65 nm commercial process design kit (PDK) calibrated for 77 K under silicon measurements. For simulating the STT-MRAMs, our study uses state-of-the-art SMTJ and DMTJ Verilog-A compact models [19,20]. The results presented within this study are based on comprehensive bitcell-level simulations carried out through exhaustive Monte Carlo simulations.…”

Section: Deep Space Electronicsmentioning

confidence: 99%

“…The simulations of the STT-MRAMs use state-of-the-art Verilog-A SMTJ and DMTJ compact models [19,20], with major device parameters that are presented in Table 2. The STT-MRAM compact models are based on physical parameters, which were characterized with experimental prototypes at 300 K. The impact of the cryogenic temperature is taken into account according to the formulations provided in [17].…”

Section: Simulation Analysis At Cryogenic Temperaturesmentioning

confidence: 99%

Embedded Memories for Cryogenic Applications

2021

Self Cite

View full text Add to dashboard Cite

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

show abstract

Compact Modeling of Perpendicular STT-MTJs With Double Reference Layers

Cited by 30 publications

References 31 publications

Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

Ultralow Voltage FinFET- Versus TFET-Based STT-MRAM Cells for IoT Applications

Relaxing non-volatility for energy-efficient DMTJ based cryogenic STT-MRAM

Embedded Memories for Cryogenic Applications

Contact Info

Product

Resources

About