Comparison of constant coefficient multipliers for CSD and Booth recoding

Hu, Anliang; Al-Khalili, A.J.

doi:10.1109/icm-02.2002.1161498

Cited by 4 publications

(3 citation statements)

References 6 publications

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“…A fully parallel high speed implementation is likewise not feasible. In [15] the authors compare the implementation of constant coefficient multipliers using CSD and Booth Recoding. Both constant codings reduce the number of partial products and hold a chance to find reusable three digit patterns in the recoded constant.…”

Section: Introductionmentioning

confidence: 99%

Reduction of partial product matrix for high-speed single or multiple constant multiplication

Faust

Chang

2010

2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

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Multiplication by one or several constants is a frequently required arithmetic operation in many DSP functions. A fast and low power implementation for single constant multiplication based on Canonical Signed Digit (CSD) was proposed by Pai et al. to extend it for multiple constant multiplication, two upper bounds for the number of partial product rows were derived. The general upper bound depends only on the bit width of the variable and the specific upper bound depends on both the bit width of the variable and the number of nonzero digits of the CSD encoded constant. Their implications on the logic depth for the carry propagate adder implementation and the depth of the carry save adder tree are analyzed. This paper present an interesting fact that if the constant requires more nonzero digits to be represented than the input bit width, the number of partial product rows can be reduced and leads to a faster and simpler implementation than the direct CSD implementation. The improvements in terms of the maximal possible and average partial product rows are also shown for some constant coefficient FIR filters examples, where the reduction ranges from none to 71% depending on the input bit width. Besides the reduction in the height of the partial product matrix, an example is also presented to show that up to 56% of full and half adders can be shared for multiple constant multiplication.

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Section: Introductionmentioning

confidence: 99%

Reduction of partial product matrix for high-speed single or multiple constant multiplication

Faust

Chang

2010

2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia)

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“…It has shown that for any n bit multiplication with CSD coefficient, the total number of addition, subtraction and shift operations never exceed by n/2 [36]. There are different types of CSD multiplier is designed in literature such as constant coefficient CSD multiplier [59], [63], low error fixed width multiplier [61], [62] etc. In constant coefficient multiplier, the coefficient is constant which provides the opportunity to design a system with low space and high speed.…”

Section: Model Of a Neuronmentioning

confidence: 99%

Application of neural networks with CSD coefficients for human face recognition

Parvin

Ahmadi

Muscedere

2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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“…A fully parallel high speed implementation is likewise not feasible. In [162], the authors compare the implementation of constant coefficient multipliers using CSD and Booth Recoding. Both constant codings reduce the number of partial products and hold a chance to find reusable three digit patterns in the recoded constant.…”

Section: Reduction Of Partial Product Matrix For High-speed Single Ormentioning

confidence: 99%

Design methodologies for complexity reduction of FIR filters

Faust¹

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SA block optimization are also proposed. By making use of the existing registers in the tapdelay line of SA block, only a small percentage of additional registers need to be introduced to allows for pipelining. A new method has also be introduced to gradually reduce the bit width of the operators in the SA block towards the output with a very small sacrifice of the output precision. Finally, very high-speed circuit architectures for the conversions from Binary to Canonical Signed Digit (CSD) and from CSD to Binary representations are proposed. These components can be used to speed up and simplify the implementation of adaptive filters.

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Comparison of constant coefficient multipliers for CSD and Booth recoding

Cited by 4 publications

References 6 publications

Reduction of partial product matrix for high-speed single or multiple constant multiplication

Reduction of partial product matrix for high-speed single or multiple constant multiplication

Application of neural networks with CSD coefficients for human face recognition

Design methodologies for complexity reduction of FIR filters

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