Comparison of Soi Versus Bulk Silicon Substrate Crosstalk Properties for Mixed-Mode IC's

Rahim, Mohamad Kamal A.; Hwang, Bor-Yuan; Foerstner, J.

doi:10.1109/soi.1992.664844

Cited by 25 publications

(3 citation statements)

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“…Also, in [23] simulation results showed that an isolated p-well (two nested wells) could provide 15 dB of isolation. Regarding SOI technology, simulation results in [24] and [10] showed negligible added isolation 2 compared to a standard high-resistive bulk, while [25] showed a noise reduction of 20 dB.…”

Section: Isolation With Horizontal Layersmentioning

confidence: 97%

Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC

2003

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Crosstalk propagating through the silicon substrate is a serious limiting factor on the performance of advanced mixed analog-digital CMOS integrated circuits. This problem also appears in RF chips in the form of power leakage from local oscillators or power amplifiers, as well as noise coupled from the digital baseband circuitry. Several studies have presented measurements on simple test structures to determine the best approach to minimize this leakage. Nevertheless, these studies are usually restricted to a single technology, and the consequences of applying results to other technologies are not evaluated. Also, these studies are usually performed with on-wafer samples, and thus package effects are not taken into account. However, package parasitics are an important factor in substrate crosstalk, since they determine how much of the leakage finds a return path to external ground. In this paper, we discuss different technological approaches to increase isolation between coupled circuits. Measurements of the isolation on some test structures fabricated in a CMOS RF technology are presented. The package parasitics effect is evaluated by comparing on-wafer vs packaged samples. Measurement results are complemented with simulations of a broader range of situations.

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Section: Isolation With Horizontal Layersmentioning

confidence: 97%

Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC

2003

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“…Future systems will require densely-packed circuits operating at high frequency. Previous approaches to reduce substrate crosstalk include guard rings [1]- [3], SOI substrates [2]- [5], high-resistivity SIMOX substrates [6]- [8], junction-isolated wells [2]- [4], and metal-filled trenches [9]. Most significant results have come from junction isolation with guard rings, which reduced crosstalk by about 28 dB over bulk Si at 1 GHz when isolating both transmitter and receiver [3], and metal-filled trenches, which have demonstrated about 30 dB of isolation at 5 GHz and greater [9].…”

Section: A Faraday Cage Isolation Structure For Substratementioning

confidence: 99%

A Faraday cage isolation structure for substrate crosstalk suppression

Scholvin

Alamo

et al. 2001

IEEE Microw. Wireless Compon. Lett.

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Abstract-We have exploited a recently-developed, through-wafer via technology in silicon to implement a novel Faraday cage scheme for substrate crosstalk suppression in system-on-chip (SOC) applications. The Faraday cage structure consists of a ring of grounded vias encircling sensitive or noisy portions of a chip. The via technology features high aspect ratio, through-wafer holes filled with electroplated Cu and lined with a silicon nitride barrier layer. The new Faraday cage structure has shown crosstalk suppression of 40 dB at 1 GHz and 36 dB at 5 GHz at a distance of 100 m. This is about 10 dB better than any other isolation technique previously reported.

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“…

AbstractTherefore, the study of the coupling characteristics of the substrate as well as the crosstalk and noise reduction techniques, are becoming more and more important [3]. Many investigations have demonstrated and explained the great interest of SOI devices for substrate crosstalk reduction [4][5].

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confidence: 99%

Interconnect mode conversion in high-speed VLSI circuits

Quéré

LeGouguec

Martin

et al.

SCS 2003. International Symposium on Signals, Circuits and Systems. Proceedings (Cat. No.03EX720)

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Therefore, the study of the coupling characteristics of the substrate as well as the crosstalk and noise reduction techniques, are becoming more and more important [3]. Many investigations have demonstrated and explained the great interest of SOI devices for substrate crosstalk reduction [4][5]. Nevertheless, the optimization of the substrate behavior from a crosstalk point of view is not the only way to do it. Circuit design rules can also reduce the risk of substrate crosstalk [6]. In this context, it is well known that it is better to design analog differential devices. For digital circuits, due to logical and physical considerations, designers put ground lines near signal ones and within the same metal layer to get a differential configuration rather than a common one. This case is illustrated in Fig.1b, where arrows depict the coupling between the two wires. From an electromagnetic point of view, it means that one should excite the differential (odd mode) mode rather than the common one (even mode): in the latter, the substrate acts as a ground plane, and thus the return longitudinal currents in the substrate as well as the shunt currents can both give rise to a significant substrate crosstalk.

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Comparison of Soi Versus Bulk Silicon Substrate Crosstalk Properties for Mixed-Mode IC's

Cited by 25 publications

References 0 publications

Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC

Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC

A Faraday cage isolation structure for substrate crosstalk suppression

Interconnect mode conversion in high-speed VLSI circuits

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