Abstract-In order to minimize ground inductance in RFICs, we have developed a high-aspect ratio, through-wafer interconnect (or substrate via) in silicon that features a silicon nitride barrier liner and completely filled Cu core. We have fabricated vias with a nominal aspect ratio of 30 and verified the integrity of the insulating liner in vias with an aspect ratio of eight. The inductance of vias with nominal aspect ratios between three and 30 approach the theoretically expected values. This interconnect technology was exploited in a novel Faraday cage structure for substrate crosstalk suppression in system-on-chip applications. The isolation structure consists of a ring of grounded vias that surrounds sensitive or noisy portions of a chip. This Faraday cage structure has shown noise suppression of 30 dB at 10 GHz and 16 dB at 50 GHz at a distance of 100 m when compared to the reference structure.Index Terms-Ground inductance, Si RF technology, substrate noise, substrate via, system-on-chip (SOC), three-dimensional interconnects, through-wafer interconnect.

We have developed a novel high-aspect ratio substrate-via technology in silicon that features a SiN insulator liner. In this technology, the via is completely filled with electroplated Cu. We have demonstrated vias with an aspect ratio of 30 and we have verified the integrity of the liner in vias with an aspect ratio of 8. The impedance of individual vias was measured in the microwave regime using a high-frequency test structure. The measured inductance of vias with aspect ratios between 3 and 30 approach the theoretically expected values.

Abstract-We have exploited a recently-developed, through-wafer via technology in silicon to implement a novel Faraday cage scheme for substrate crosstalk suppression in system-on-chip (SOC) applications. The Faraday cage structure consists of a ring of grounded vias encircling sensitive or noisy portions of a chip. The via technology features high aspect ratio, through-wafer holes filled with electroplated Cu and lined with a silicon nitride barrier layer. The new Faraday cage structure has shown crosstalk suppression of 40 dB at 1 GHz and 36 dB at 5 GHz at a distance of 100 m. This is about 10 dB better than any other isolation technique previously reported.

The reduction of ground inductance is crucial to the gain of RF and microwave circuits. To provide a low-inductance interconnect, we have developed a through-wafer via technology in silicon that incorporates a silicon nitride barrier liner and is filled with electroplated Cu.We have demonstrated vias with an aspect ratio as high as 14 and an inductance that approaches the theoretically expected value. Using the same technology, we have implemented a novel Faraday cage scheme for on-chip subsystem isolation that is successful in suppressing crosstalk by over 20 dB at 1 GHz at a distance of 100 pm.-

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