A high aspect-ratio silicon substrate-via technology and applications: through-wafer interconnects for power and ground and Faraday cages for SOC isolation

Abstract

The reduction of ground inductance is crucial to the gain of RF and microwave circuits. To provide a low-inductance interconnect, we have developed a through-wafer via technology in silicon that incorporates a silicon nitride barrier liner and is filled with electroplated Cu.We have demonstrated vias with an aspect ratio as high as 14 and an inductance that approaches the theoretically expected value. Using the same technology, we have implemented a novel Faraday cage scheme for on-chip subsystem isolation that is successful in suppressing crosstalk by over 20 dB at 1 GHz at a distance of 100 pm.-

A Faraday cage isolation structure for substrate crosstalk suppression

“…In our first implementation, we used a 77-m thick substrate and 10-m diameter vias with an aspect ratio close to 8. Via spacing varies between 10 and 70 m. Initial results presented in [10] revealed that the crosstalk through the air between the microwave probes masked the true crosstalk suppression of the Faraday cages. In these new measurements, we have introduced a grounded metallic screen between the two probes, which has reduced the air crosstalk by about 30 dB.…”

“…1). The basic fabrication process described in [10], [11] consists of a Bosch RIE silicon etch to form high-aspect ratio via holes, PECVD silicon nitride for the insulating liner, and electroplated Cu to fill the vias. Cu CMP is used to smooth the top of the Cu vias after electroplating.…”

“…By exploiting a high-aspect ratio, substrate-via technology we recently developed [10], [11], the Faraday cage exhibits a small footprint. The Faraday cage consists of a ring of grounded substrate vias that encircle a noisy or sensitive circuit.…”

IC-compatible two-level bulk micromachining process module for RF silicon technology

“…This, however, still limits the compactness of the spiral coil of the inductor, since a hollow coil design is required. Most effective would be to use an anisotropic dry etching of the via to reduce the surface area [5]. For the given spacing of the inductor coil from the chip surface an about ten-fold reduction of the via parasitic capacitance can be expected.…”

“…1(a)]. Several groups have proposed wafer thinning to a substrate thickness of 100-200 m, which would allow for through-wafer vias, but would raise serious concerns about wafer handling and stability during the manufacturing process [4], [5]. The significance of a well-defined ground under a spiral inductor coil on silicon substrates in 2) has not been widely recognized yet.…”