Complementary tunneling transistor for low power application

Wang, P.-F.; Hilsenbeck, K.; Nirschl, T.; Oswald, Maria Elisabeth; Stepper, Ch.; Weis, Mirjam; Schmitt‐Landsiedel, D.; Hänsch, W.

doi:10.1016/j.sse.2004.04.006

Cited by 456 publications

(180 citation statements)

References 10 publications

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“…unnel field-effect transistors (TFET) are attracting wide attention because of their low subthreshold swing and low OFF-state leakage current [1][2][3][4][5][6][7][8]. Since the channel current is controlled by the tunneling mechanism on the source side, TFETs are more immune to short-channel effects (such as V T roll-off) unlike the conventional nanoscale MOSFETs [9][10][11].…”

Section: Introductionmentioning

confidence: 99%

“…The presence of doped source and drain regions in TFETs also necessitates a complex thermal budget due to the need for ion implantation and expensive thermal annealing techniques [20][21][22]. Abrupt junctions are essential for efficient tunneling in TFETs [1,2,7]. However, creating abrupt junctions using high temperature processes is not easy due to the diffusion of the dopant atoms from the source/drain regions into the channel.…”

Section: Introductionmentioning

confidence: 99%

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Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Kumar

Janardhanan

2013

IEEE Trans. Electron Devices

566

249

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Abstract-Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Further, fabrication of doping-less TFET does not require high-temperature doping/annealing processes and therefore, cuts down the thermal budget opening up the possibilities for fabricating TFETs on single crystal silicon-onglass substrates formed by wafer scale epitaxial transfer.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Kumar

Janardhanan

2013

IEEE Trans. Electron Devices

566

249

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“…Fig. 9 shows that RUTFET has excellent scalability without any degradation of SS and draininduced barrier thinning (DIBT) [29,30,31,32,33] since its main channel length is defined along with vertical direction. Moreover, the I OFF slightly decrease due to the decrease of SRH (Shockley-Read-Hall) current while I ON increases with the help of reduced channel resistance (R CH ).…”

Section: Scalability Of Rutfetmentioning

confidence: 99%

Reconfigurable U-shaped tunnel field-effect transistor

Lee

kwon

Choi

et al. 2017

IEICE Electron. Express

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A reconfigurable U-shaped tunnel field-effect transistor (RUT-FET) is proposed as a low-power dynamically programmable logic device. It has several advantages over conventional reconfigurable TFETs: 1) Excellent scalability without any degradation of subthreshold swing (SS) and draininduced barrier thinning (DIBT) with recessed channel structure. 2) High current drivability with increased band-to-band tunneling junction 3) Scaling of SS with tunneling barrier width defined by geometrical parameters. In this manuscript, its electrical characteristics are examined by technology computer-aided design (TCAD) simulation. It shows ∼30× higher ON-state current than control devices and 41.8 mV/dec-SS during drain current increase by five orders magnitude. The reconfigurable operations for nand p-type FETs are also discussed.

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“…The tunnel FET [41][42][43] is a gated p−i−n diode with a gate over the intrinsic region; it exploits the gate controlled electron tunneling from the valence band of the p-region to the conduction band of the i-region for reversed biases, resulting in very abrupt off-on transition. They have been reported on Si, III-V and CNT alternatives.…”

Section: Small Slope Switchesmentioning

confidence: 99%

New Semiconductor Devices

Balestra

2008

Acta Phys. Pol. A

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A review of recently emerging semiconductor devices for nanoelectronic applications is given. For the end of the international technology roadmap for semiconductors, very innovative materials, technologies and nanodevice architectures will be needed. Silicon on insulator-based devices seem to be the best candidates for the ultimate integration of integrated circuits on silicon. The flexibility of the silicon on insulator-based structure and the possibility to realize new device architectures allow to obtain optimum electrical properties for low power and high performance circuits. These transistors are also very interesting for high frequency and memory applications. The performance and physical mechanisms are addressed in single-and multi-gate thin film Si, SiGe and Ge metal-oxide-semiconductor field-effect-transistors. The impact of tensile or compressive uniaxial and biaxial strains in the channel, of high k materials and metal gates as well as metallic Schottky source-drain architectures are discussed. Finally, the interest of advanced beyond-CMOS (complementary MOS) nanodevices for long term applications, based on nanowires, carbon electronics or small slope switch structures are presented.

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Complementary tunneling transistor for low power application

Cited by 456 publications

References 10 publications

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

Reconfigurable U-shaped tunnel field-effect transistor

New Semiconductor Devices

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