2015
DOI: 10.1109/tns.2014.2373362
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Component Prototypes Towards a Low-Latency, Small-Form-Factor Optical Link for the ATLAS Liquid Argon Calorimeter Phase-I Trigger Upgrade

Abstract: This paper presents several component prototypes towards a low-latency, small-form-factor optical link designed for the ATLAS Liquid Argon Calorimeter Phase-I trigger upgrade. A prototype of the custom-made dual-channel optical transmitter module, the Miniature optical Transmitter (MTx), with separate transmitter optical sub-assemblies (TOSAs) has been demonstrated at data rates up to 8 Gbps per channel. A Vertical-Cavity Surface-Emitting Laser (VCSEL) driver ASIC has been developed and is used in the current … Show more

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Cited by 10 publications
(3 citation statements)
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“…Signal loss through the cables is compensated by three quad-channel signal repeaters (DS100BR410, TI Inc.), and compensated serial links are received by a low-cost Xilinx Artix-7 FPGA (XC7A200TFFG1156). The FPGA is the central component of the Router, it decodes the serial links, performs fixed-latency 12-to-4 cut-through switching [3], suppresses NULL packets, and forwards selected data packets to the Optical Transceivers (Tx) [5]. In addition, there are slow control and monitoring interfaces with the GBT-SCA [6]; clock fan-out and distribution with a low jitter LVDS buffer (CDCLVD1212, TI Inc.); a flash memory (S25FL256S, Cypress Inc.) for on-board configuration; and DC-DC converters with the FEAST ASIC [7].…”
Section: Radiation Requirement For the Router 21 Overview Of The Routermentioning
confidence: 99%
“…Signal loss through the cables is compensated by three quad-channel signal repeaters (DS100BR410, TI Inc.), and compensated serial links are received by a low-cost Xilinx Artix-7 FPGA (XC7A200TFFG1156). The FPGA is the central component of the Router, it decodes the serial links, performs fixed-latency 12-to-4 cut-through switching [3], suppresses NULL packets, and forwards selected data packets to the Optical Transceivers (Tx) [5]. In addition, there are slow control and monitoring interfaces with the GBT-SCA [6]; clock fan-out and distribution with a low jitter LVDS buffer (CDCLVD1212, TI Inc.); a flash memory (S25FL256S, Cypress Inc.) for on-board configuration; and DC-DC converters with the FEAST ASIC [7].…”
Section: Radiation Requirement For the Router 21 Overview Of The Routermentioning
confidence: 99%
“…For example, during flooding or heavy rain, wires may become wet and thus provide poor signals, while wireless communication can be made to be more immune to water damage. As presented in Figure 8, the wireless communication hardware development can leverage our previous R&D works in which we have demonstrated a wideband cognitive radio transceiver and wireless channel emulator through a National Science Foundation (NSF)-funded project [10], a radiation-hard 6-12 GHz 00.37pS RMS jitter wideband LC-VCO phase-locked loop (PLL) [11], and radiationtolerant application specific integrated circuits (ASICs) for CERN's large hadron collider (LHC) detectors [12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27]. In developing the wireless transceiver, commercial off-the-shelf (COTS) radiationhardened components based on Silicon-on-Sapphire (SOS) and Silicon on Insulator (SOI) technology should be utilized.…”
Section: Wireless Cnfa Sensormentioning
confidence: 99%
“…The trigger signals are transmitted by customized optical transceivers at 5.12 Gbps. These devices include the dual-channel miniature optical transmitters (MTx) and transceivers (MTRx) [4,5]. The LAr upgrade requires (including spares) 3240 MTx and 810 MTRx modules for data transmission and clock/control signals, respectively, being installed on 150 LAr Trigger Digitizer Boards (LTDBs) [6].…”
Section: Introductionmentioning
confidence: 99%