Computer-aided redesign of VLSI circuits for hot-carrier reliability

Li, P.-C.; Hajj, I.N.

doi:10.1109/iccd.1993.393320

Cited by 9 publications

(8 citation statements)

References 26 publications

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“…The effective switching can be changed only by rewiring the netlist. Another HCE effect concerning the ordering of transistors has been observed in [12] and [15]. For example, in Fig.…”

Section: B Problem Formulationmentioning

confidence: 84%

“…This goal targets improvement of the mean-time-to-failure (MTTF) under the assumption that if any device in the circuit fails, the whole circuit fails. The other category of techniques includes the method proposed by Li et al, which performs input pin reordering and gate resizing [15] to minimize the impact of performance degradation on the entire circuit. The idea is that not all devices in the circuit are of equal importance as far as overall performance is concerned.…”

Section: Delay-constrained Reliability Optimizationmentioning

confidence: 99%

“…For example, input slew rate to a transistor and effective output switching are identified as the most important factors [12], [15] determining device degradation. Due to the resistive behavior of deep submicron interconnects, estimation of slew rates at the gate level is very inaccurate when the placement and routing information is unknown.…”

Section: Delay-constrained Reliability Optimizationmentioning

confidence: 99%

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Fast postplacement optimization using functional symmetries

Chang

Hsiao

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The timing-convergence problem arises because estimations made during logic synthesis may not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement solution is left intact throughout the optimization. A linear-time algorithm is proposed to detect functional symmetries in the Boolean network which are then used as the basis for rewiring. Integration with an existing gate-sizing algorithm further proves the effectiveness of our technique. Three applications are demonstrated: delay, power, and reliability optimization.

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“…The effective switching can be changed only by rewiring the netlist. Another HCE effect concerning the ordering of transistors has been observed in [12] and [15]. For example, in Fig.…”

Section: B Problem Formulationmentioning

confidence: 84%

Section: Delay-constrained Reliability Optimizationmentioning

confidence: 99%

Section: Delay-constrained Reliability Optimizationmentioning

confidence: 99%

See 1 more Smart Citation

Fast postplacement optimization using functional symmetries

Chang

Hsiao

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…However, there exists no such tool which consider reliability early during the design process. Recently, Li and Hajj [17] have been able to use input reordering at the circuit level to eliminate the hot carrier effect degradation on performance. Sun, Leblebici, artd Kang have used macro-models for evaluating hot-carrier related degradations of simple C160S circuits [15].…”

Section: Introductionmentioning

confidence: 99%

Logic synthesis for reliability: an early start to controlling electromigration and hot-carrier effects

Roy

Prasad

1995

IEEE Trans. Rel.

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Designing reliable CMOS chips involve careful circuit design with attention directed to some of the potential reliability problems such as electromigration and hot carrie:r effects. This paper considers logic synthesis to handle electromigration and hot carrier degradation early in the design. phase. The electromigration and the hot carier effects are est,imated at the gate level using signal activity measure, which is the average number of transitions at circuit nodes. Logic can be optimally synthesized suited for different applications requiring different types of inputs for higher reliability and low silicon area. Results have been obtained for MCNC syntk~esis benchmark examples.

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“…At the device level, techniques for optimizing hotcarrier reliability include using high quality oxide and lightly doped drain (LDD) MOSFETs [8]. At the circuit level, hot-carrier resistant re-design techniques have been developed [16].…”

Section: Introductionmentioning

confidence: 99%

Switch level hot-carrier reliability enhancement of VLSI circuits

Dasgupta

Karri

Proceedings of International Workshop on Defect and Fault Tolerance in VLSI

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Long-term reliability of MOS VLSI circuits is becoming an important issue with rapid advances in VLSI technology and increasing VLSI chip densities. Hot-carrier effects and electromigration are the two important failure mechanisms that significantly impact the long-term reliability of high-density VLSI ICs. In this paper, we present a probabilistic switch-level method for identifying MOSFETs in the circuit that are most susceptible to hot-carrier effects. Subsequently, we outline two techniques -(i) reordering of inputs to logic gates and (SI selective MOSFET sizing -to reduce the hot-carrier susceptibility of these critical MOSFETs. Finally, we show that for a given circuit, the best design in terms of hot-carrier reliability does not necessarily coincide with the best design in terms of power consumption. The algorithms are incorporated into SIS and are evaluated on the ISCAS-MCNC91 benchmark suite.

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Computer-aided redesign of VLSI circuits for hot-carrier reliability

Cited by 9 publications

References 26 publications

Fast postplacement optimization using functional symmetries

Fast postplacement optimization using functional symmetries

Logic synthesis for reliability: an early start to controlling electromigration and hot-carrier effects

Switch level hot-carrier reliability enhancement of VLSI circuits

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