Computer Architecture

Mueller, Silvia Melitta; Paul, Wolfgang J.

doi:10.1007/978-3-662-04267-0

Cited by 54 publications

(43 citation statements)

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“…This library was then used in the verification of IEEE-compliant floating-point arithmetic algorithms [5] and hardware units [6]. Berg et al [3] have formally verified a theory of IEEE rounding presented in [32] using the theorem prover PVS. They have used a formal definition of rounding based on Miner's formalization of the standard [29].…”

Section: Related Workmentioning

confidence: 99%

Formalization of Fixed-Point Arithmetic in HOL

Akbarpour

Tahar

Dekdouk

2005

Form Method Syst Des

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Abstract. This paper addresses the formalization in higher-order logic of fixed-point arithmetic. We encoded the fixed-point number system and specified the different quantization modes in fixed-point arithmetic such as the directed and even quantization modes. We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An error analysis is then performed to check the correctness of the quantized result after carrying out basic arithmetic operations, such as addition, subtraction, multiplication and division against their mathematical counterparts. Finally, we showed by an example how this formalization can be used to enable the verification of the transition from floating-point to fixed-point algorithmic level in the signal processing design flow.

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Section: Related Workmentioning

confidence: 99%

Formalization of Fixed-Point Arithmetic in HOL

Akbarpour

Tahar

Dekdouk

2005

Form Method Syst Des

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“…We have specified and verified the designs on the gate level in PVS. The paper-and-pencil proofs in [41] served as guidelines for the formal proofs. Only small changes to the designs were necessary-some due to errors in [41], some to slightly simplify the proofs-with negligible impact on hardware cost and cycle time.…”

Section: Introductionmentioning

confidence: 99%

“…The FPU design is taken from the textbook on computer architecture by Müller and Paul [41], where the designs are described on the level of single gates. The correctness of the circuits is proved in a mathematical textbook fashion.…”

Section: Introductionmentioning

confidence: 99%

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Formal Verification of the VAMP Floating Point Unit

Jacobi

Berg

2005

Form Method Syst Des

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We report on the formal verification of the floating point unit used in the VAMP processor. The dualprecision FPU is IEEE compliant and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions.We have formalized the IEEE standard 754. The formalization is supplemented by a rich theory of rounding, which includes notations and theorems facilitating the verification of the actual hardware. The theory of rounding enables the separation of the hardware into smaller modules which can be verified individually. Each module is verified on the gate level against a formal specification. The combination of these formal specifications, together with the theorems from the theory of rounding, yield the overall correctness of the FPU, i.e., theorems stating that the gate-level hardware complies with the high-level formalization of the IEEE standard. The verification is done completely in the theorem prover PVS.We further report on the implementation and test of the verified FPU on a Xilinx FPGA.

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“…We consider the following standard models for languages: (i) the model of the machine language / instruction set architecture (ISA) of the VAMP [11,12], a variant of the DLX architecture [13], (ii) the model of VAMP assembler, (iii) the semantics of C0, which is the subset of C we use [14], and (iv) the semantics of C0A, which is C0 with in line assembler code. In the latter model, we have to consider both the computation of a (compiled) C0 program and of an assembler program.…”

Section: Computational Modelsmentioning

confidence: 99%

On the Architecture of System Verification Environments

Hillebrand

Paul

Hardware and Software: Verification and Testing

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Abstract. Implementations of computer systems comprise many layers and employ a variety of programming languages. Building such systems requires support of an often complex, accompanying tool chain.The Verisoft project deals with the formal pervasive verification of computer systems. Making use of appropriate formal specification and proof tools, this task requires (i) specifying the layers and languages used in the implementation, (ii) specifying and verifying the algorithms employed by the tool chain (or, alternatively, validating their actual output), and (iii) proving simulation statements between layers, arguing about the programs residing at the different layers. Combining the simulation statements for all layers should allow to transfer correctness results for top-layer programs to their bottom-layer representation; in this manner, a verified stack can be built.Maintaining all formal artifacts, the actual system implementation, and the (verification) tool chain is a challenging task. We call sets of tools that help addressing this task system verification environments. In this paper, we describe the structure, contents, and architecture of the system verification environment used in the Verisoft project.

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Computer Architecture

Cited by 54 publications

References 0 publications

Formalization of Fixed-Point Arithmetic in HOL

Formalization of Fixed-Point Arithmetic in HOL

Formal Verification of the VAMP Floating Point Unit

On the Architecture of System Verification Environments

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