Computing Architectural Vulnerability Factors for Address-Based Structures

Biswas, Arijit; Racunas, Paul; Cheveresan, Razvan; Emer, Joel; Mukherjee, S.; Rangan, Ram

doi:10.1109/isca.2005.18

Cited by 143 publications

(18 citation statements)

References 11 publications

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“…The irradiation impact is reduced when the benchmarks are executed with a deactivated cache (mapping utility knob of the 68882 coprocessor). Similarly, in Biswas et al [2005], we see different AVF values for the considered benchmark applications. A paper that deals with the impact of ported SW on reliability metrics is Kim et al [2011].…”

Section: Violationsmentioning

confidence: 68%

Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations

Rodopoulos¹,

Psychou

Sabry

et al. 2015

ACM Comput. Surv.

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Technology downscaling is expected to amplify a variety of reliability concerns in future digital systems. A good understanding of reliability threats is crucial for the creation of efficient mitigation techniques. This survey performs a systematic classification of the state of the art on the analysis and modeling of such threats, which are caused by physical mechanisms to digital systems. The purpose of this article is to provide a classification tool that can aid with the navigation across the entire landscape of reliability analysis and modeling. A classification framework is constructed in a top-down fashion from complementary categories, each one addressing an approach on reliability analysis and modeling. In comparison to other classifications, the proposed methodology approaches the target research domain in a complete way, without suppressing hybrid works that fall under multiple categories. To substantiate the usability of the classification framework, representative works from the state of the art are mapped to each appropriate category and are briefly analyzed. Thus, research trends and opportunities for novel approaches can be identified.

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Section: Violationsmentioning

confidence: 68%

Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations

Rodopoulos¹,

Psychou

Sabry

et al. 2015

ACM Comput. Surv.

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“…Some of these studies use faultinjection campaigns [9,66,72,75]. Others use offline-analysis based estimation [73,88,95,98] and runtime-only estimation [35,79,93] approaches.…”

Section: Methods For Computing Reliability Metricsmentioning

confidence: 99%

“…Biswas et al [35] present lifetime analysis approach for computing AVF of address-based structures, such as data cache, data translation buffer and store buffer. Whether a bit in the cache is ACE depends on the sequence of accesses to the cache.…”

Section: Methods For Computing Reliability Metricsmentioning

confidence: 99%

“…While the simulators provide the flexibility to experiment with certain components, techniques or fault-injection campaigns within reasonable amount of time and in a repeatable manner, their modeling inaccuracies and simplifying assumptions may lead to misleading conclusions. On the other hand, while the field studies on real machines provide valuable [3,36,37,41,46,48,53,54,61,62,66,79,80,91,[94][95][96][97] Computing reliability metrics [9,35,66,72,73,75,88,93,95,98] Use of compiler [38, 43, 49, 60-62, 65, 77, 79, 89, 97, 99] Use of redundancy/duplication [8,27,28,44,50,51,55,58,59,64,68,71,73,76,77,90,96,[99][100]…”

Section: A Background On and Classifica-tion Of Techniques For Reliabmentioning

confidence: 99%

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A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

Mittal

Vetter

2016

IEEE Trans. Parallel Distrib. Syst.

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Recent trends of aggressive technology scaling have greatly exacerbated the occurrences and impact of faults in computing systems. This has made 'reliability' a first-order design constraint. To address the challenges of reliability, several techniques have been proposed. This paper provides a survey of architectural techniques for improving resilience of computing systems. We especially focus on techniques proposed for microarchitectural components, such as processor registers, functional units, cache and main memory etc. In addition, we discuss techniques proposed for non-volatile memory (NVM), GPUs and 3D-stacked processors. To underscore the similarities and differences of the techniques, we classify them based on their key characteristics. We also review the metrics proposed to quantify vulnerability of processor structures. We believe that this survey will help researchers, system-architects and processor designers in gaining insights into the techniques for improving reliability of computing systems.

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“…In order to estimate each cache unit SER, its Architectural Vulnerability Factor (AVF) is computed according to the life time analysis method presented in [50] and multiplied with the intrinsic alpha and neutron-induced FIT rates of a 65 nm technology SRAM cell working in terrestrial environment. The FIT rate is obtained from an industrial soft error analysis tool [51].…”

Section: A Soft Error Analysis In Srammentioning

confidence: 99%

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy

Oboril

Bishnoi

Ebrahimi

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

165

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Magnetic Random Access Memory (MRAM) is a very promising emerging memory technology because of its various advantages such as non-volatility, high density and scalability. In particular, Spin Orbit Torque (SOT) MRAM is gaining interest as it comes along with all the benefits of its predecessor Spin Transfer Torque (STT) MRAM, but is supposed to eliminate some of its shortcomings. Especially the split of read and write paths in SOT-MRAM promises faster access times and lower energy consumption compared to STT-MRAM. In this work, we provide a very detailed analysis of SOT-MRAM at both circuit-and architecture-level. We present a detailed evaluation of performance and energy related parameters and compare the novel SOT-MRAM with several other memory technologies. Our architecture-level analysis shows that a hybridcombination of SRAM for the L1-Data-cache, SOT-MRAM for the L1-Instruction-cache and L2-cache can reduce the energy consumption by 60 % while the performance increases by 1 % compared to an SRAM-only configuration. Moreover, the retention failure probability of SOT-MRAM is 27x smaller than the probability of radiation-induced Soft Errors in SRAM, for a 65 nm technology node. All of these advantages together make SOT-MRAM a viable choice for microprocessor caches.Index Terms-spin orbit torque, non-volatile memory, cache, hybrid, magnetic memory, reliability, failure rate 0278-0070 (c)

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Computing Architectural Vulnerability Factors for Address-Based Structures

Cited by 143 publications

References 11 publications

Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations

Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations

A Survey of Techniques for Modeling and Improving Reliability of Computing Systems

Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy

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