Concurrent error detection in block ciphers

Fernandez-Gomez, S.; Rodríguez-Andina, Juan J.; Mandado, Enrique

doi:10.1109/test.2000.894310

Cited by 18 publications

(4 citation statements)

References 8 publications

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“…Area overhead of this approach is due to the encoders at the input and decoders at the output to translate the plain and cipher texts into the internal code words. In [16] the plaintext is encoded by setting several bits of the message to a particular fixed value, 0 or 1, and then encrypted. A mismatch between these fixed bits of deciphered text and the original plain text detects an error.…”

Section: Ced Architectures For Symmetric Block Ciphers: Backgroundmentioning

confidence: 99%

Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers

Karri¹,

Kuznetsov

Goessel

2003

Lecture Notes in Computer Science

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Abstract. Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption algorithms. In this paper we will describe parity code based concurrent error detection (CED) approach against such attacks in substitution-permutation network (SPN) symmetric block ciphers [22]. The basic idea compares a carefully modified parity of the input plain text with that of the output cipher text resulting in a simple CED circuitry. An analysis of the SPN symmetric block ciphers reveals that on one hand, permutation of the round outputs does not alter the parity from its input to its output. On the other hand, exclusive-or with the round key and the non-linear substitution function (s-box) modify the parity from their inputs to their outputs. In order to change the parity of the inputs into the parity of outputs of an SPN encryption, we exclusive-or the parity of the SPN round function output with the parity of the round key. We also add to all s-boxes an additional 1-bit binary function that implements the combined parity of the inputs and outputs to the s-box for all its (input, output) pairs. These two modifications are used only by the CED circuitry and do not impact the SPN encryption or decryption. The proposed CED approach is demonstrated on a 16-input, 16-output SPN symmetric block cipher from [1].

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Section: Ced Architectures For Symmetric Block Ciphers: Backgroundmentioning

confidence: 99%

Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers

Karri¹,

Kuznetsov

Goessel

2003

Lecture Notes in Computer Science

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show abstract

“…Area overhead of this approach is due to the encoders at the input and decoders at the output to translate the plain and cipher texts into the internal code words. A simple encoding scheme of setting several bits of the message to a particular fixed value, 0 or 1, was proposed in [20]. A mismatch between these fixed bits of deciphered text and the original plain text detects an error.…”

Section: Fault-based Side-channel Cryptanalysismentioning

confidence: 99%

Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers

Karri

Mishra

et al. 2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

156

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Fault-based side-channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy-based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overheads (either area or performance). The authors investigate systematic approaches to low-cost low-latency CED techniques for symmetric encryption algorithms based on inverse relationships that exist between encryption and decryption at algorithm level, round level, and operation level and develop CED architectures that explore tradeoffs among area overhead, performance penalty, and fault detection latency. The proposed techniques have been validated on FPGA implementations of Advanced Encryption Standard (AES) finalist 128-bit symmetric encryption algorithms.

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“…Another CED approach involves encoding the message before encryption and checking it for errors after decryption [16]. This scheme results in significantly less area overhead as compared to other encoding schemes but has large fault detection latency and needs modification of the algorithm to improve its performance.…”

Section: Fault-based Side-channel Cryptanalysismentioning

confidence: 99%

Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers

Karri¹,

Wu²,

Mishra³

et al. 2001

Proceedings of the 38th Conference on Design Automation - DAC '01

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Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for symmetric encryption algorithms based on the inverse relationship that exists between encryption and decryption at algorithm level, round level and operation level and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations of AES finalist 128-bit symmetric encryption algorithms.

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Concurrent error detection in block ciphers

Cited by 18 publications

References 8 publications

Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers

Parity-Based Concurrent Error Detection of Substitution-Permutation Network Block Ciphers

Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers

Concurrent error detection of fault-based side-channel cryptanalysis of 128-bit symmetric block ciphers

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