Constructing a Multi-OS Platform with Minimal Engineering Cost

Kinebuchi, Yuki; Morita, Takushi; Makijima, Kazuo; Sugaya, Midori; Nakajima, Tatsuo

doi:10.1007/978-3-642-04284-3_18

Cited by 21 publications

(8 citation statements)

References 6 publications

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“…Similar approaches to implement multi-OS are shown in [5], [6], [7] and [8]. However, the approaches focus on IA-32 multicore architectures which are used for desktop computers.…”

Section: B Related Workmentioning

confidence: 96%

On a domain block based mechanism to mitigate DoS attacks on shared caches in asymmetric multiprocessing multi operating systems

Schnarz¹,

Fischer²,

Wietzke³

et al. 2014

2014 Information Security for South Africa

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Asymmetric multiprocessing (AMP) based multiOSs are going to be established in future to enable parallel execution of different functionalities while fulfilling requirements for real-time, reliability, trustworthiness and security. Especially for in-car multimedia systems, also known as InVehicle Infotainment (IVI) systems, the composition of different OS-types onto a system-on-chip (SoC) offers a wide variety of advantages in embedded system development. However, the asymmetric paradigm, which implies the division and assignment of every hardware resource to OS-domains, is not applicable to every part of a system-on-chip (SoC). Caches are often shared between multiple processors on multi processor SoCs (MP-SoC). According to their association to the main memory, OSs running on the processor cores are naturally vulnerable to DoS attacks. An adversary who has compromised one of the OS-domains is able to attack an arbitrary memory location of a co-OS-domain. This introduces performance degradations on victim's memory accesses. In this work a method is proposed which prohibits the surface for interference, introduced by the association of cache and main memory. Therefore, the contribution of this article is twofold. It introduces an attack vector, by deriving an algorithm from the cache way associativity, to affect the coOSs running on the same platform. Using this vector it is shown that the mapping of contiguous memory blocks intensifies the effect. Subsequently, a memory mapping method is proposed which mitigates the interference effects of cache coherence. The approach is evaluated by a proof-of-concept implementation, which illustrates the performance impact of the attack and the countermeasure, respectively. The method enables a more reliable implementation of AMP-based multi-OSs on MP-SoCs using shared caches without the need to modify the hardware layout.

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“…Similar approaches to implement multi-OS are shown in [5], [6], [7] and [8]. However, the approaches focus on IA-32 multicore architectures which are used for desktop computers.…”

Section: B Related Workmentioning

confidence: 96%

On a domain block based mechanism to mitigate DoS attacks on shared caches in asymmetric multiprocessing multi operating systems

Schnarz¹,

Fischer²,

Wietzke³

et al. 2014

2014 Information Security for South Africa

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“…SPUMONE (Software Processing Unit, Multiplexing ONE into two or more) is a thin software layer for multiplexing a single physical CPU core into multiple virtual cores [7,9]. The current target processor of SPUMONE is the SH4a architecture, which is very similar to the MIPS architecture, and the processor is adopted in various Japanese embedded system products.…”

Section: Fig 4: Spumone Basic Architecturementioning

confidence: 99%

Temporal and spatial isolation in a virtualization layer for multi-core processor based information appliances

Nakajima¹,

Kinebuchi²,

Shimada³

et al. 2011

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

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A virtualization layer makes it possible to compose multiple functionalities on a multi-core processor with minimum modifications of OS kernels and applications. A multi-core processor is a good candidate to compose various software independently developed for dedicated processors into one multi-core processor to reduce both the hardware and development cost. In this paper, we present SPUMONE, which is a virtualization layer suitable for developing multi-core processor based-information appliances. I IntroductionMulti-core processors are being increasingly adopted for embedded systems because they improve performance, power consumption and lower development cost. Composing multiple operating systems on a multi-core processor enhances the reusability of software when developing rich functional information appliances. Multiple OS environments enable the product to use two versions of an operating system at the same time. In order to build multiple OS environments, a virtualization layer specialized for embedded systems is necessary 1 , since most of processors for embedded systems support only two protection levels, and there is no hardware support for virtualization. In traditional approaches, an OS kernel runs at the user level to isolate the respective OS kernels to increase reliability, but this approach requires heavy modifications to the guest OSes if there is no proper hardware virtualization support that rarely exists in embedded systems. Therefore existing virtualization solutions are not preferred by the embedded system industry.In [1], Armand and Gien present several requirements for a virtualization layer to be suitable for embedded systems:i.It should run an existing operating system and its supported applications in a virtualized environment, such that modifications required to the operating system are minimized (ideally none), and performance overhead is as low as possible. ii. It should be straightforward to move from one version of an operating system to another one; this is especially important to keep up with frequent Linux evolutions. iii. It should reuse native device drivers from their existing execution environments with no modification. iv. It should support existing legacy often real-time 1 Our virtualization layer can used for various embedded systems, but our current main focus is information appliances.operating systems and their applications while guaranteeing their deterministic real-time behavior.Our project is developing SPUMONE, which is a virtualization layer for multi-core processor-based embedded systems. SPUMONE assumes to use an SMP(Symmetric Multiprocessing)-based multi-core processor, and each core has a core-local memory. Thus, it is easy to share code and data from all cores, but each core can keep some code and data secretly in a core-local memory. SPUMONE uses the characteristics to implement the spatial isolation. SPUMONE satisfies the above requirements, and currently focuses on achieving the following four goals.i.Mapping of virtual cores on physical cores dynamically ...

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“…Therefore, in order to achieve better real-time responsiveness especially for some real-time tasks in a GPOS, we conduct a vCPU priority-boosting and migration mechanism in this paper, and discuss and compare it with other works. All the works are based on the previous developed virtualization work named SPUMONE [3] [4].…”

Section: Mixed Priority Scheduling In Virtualizationmentioning

confidence: 99%

“…The hypervisor 3 can use these additional computing resources to achieve better performance by managing them in proper ways, such as power management and so on. This kind of usage is also gaining more attentions in the CPS (Cyber-Physical System) environment with their diverse application fields.…”

Section: Introductionmentioning

confidence: 99%

Improving GPOS real-time responsiveness using vCPU migration in an embedded multicore virtualization platform

Lin

Mitake

Nakajima

2013

2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications

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In this paper, a vCPU (virtual CPU) migration mechanism in order to improve real-time responsiveness in a GPOS (General Purpose Operating System) is presented in the embedded multicore virtualization platform and can also be applied to CPS environment.In a GPOS/RTOS (Real Time Operating System) virtualization system nowadays, tasks in GPOS, however, also need some degree of real-time services from the system. Unfortunately, in a traditional virtualization platform, a virtualization layer always gives RTOS vCPU higher priority and preempts the execution of GPOS. Therefore, a kernel module in the GPOS is added in our virtualization system to export and boost a GPOS vCPU contexts which needs higher priority against RTOS vCPU. At the same time, in order not to sacrifice the performance of the victim RTOS vCPU, a vCPU migration mechanism is added to our virtualization system, and migrates the RTOS vCPU to a low-loading CPU when this vCPU is preempted.Performance improvement of GPOS's real-time responsiveness is also given while a detailed analysis of the overhead of the RTOS vCPU is performed as well. 978-1-4799-0850-9/13/$31.00 ©2013 IEEE

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Constructing a Multi-OS Platform with Minimal Engineering Cost

Cited by 21 publications

References 6 publications

On a domain block based mechanism to mitigate DoS attacks on shared caches in asymmetric multiprocessing multi operating systems

On a domain block based mechanism to mitigate DoS attacks on shared caches in asymmetric multiprocessing multi operating systems

Temporal and spatial isolation in a virtualization layer for multi-core processor based information appliances

Improving GPOS real-time responsiveness using vCPU migration in an embedded multicore virtualization platform

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