COOLMOS/sup TM/-a new milestone in high voltage power MOS

Lorenz, L.; Deboy, G.; Knapp, Alfred; März, Martin

doi:10.1109/ispsd.1999.764028

Cited by 194 publications

(67 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Cependant, cet inconvénient est plus que compensé par le fort niveau de dopage de ces bandes N, de telle sorte que la résistance passante spécifique de ces nouveaux composants est très inférieure à celle des composants conventionnels équivalents : à titre d'exemple, pour une tenue en tension de 600 Volts, un transistor COOLMOS™ présente une résistance passante spécifique 5 fois plus faible que celle d'un transistor VDMOS conventionnel à zone de drift uniforme [26] : cette valeur est même inférieure à la limite des composants VDMOS conventionnels.…”

Section: I51 Les Composants à Superjonctionunclassified

Conception de transistors MOS haute tension (1 200 volts) pour l'électronique de puissance

Théolier

2010

E.J.E.E

View full text Add to dashboard Cite

Section: I51 Les Composants à Superjonctionunclassified

Conception de transistors MOS haute tension (1 200 volts) pour l'électronique de puissance

Théolier

2010

E.J.E.E

View full text Add to dashboard Cite

“…Indeed, this principle allows to overcome the 'breakdown voltage/on-state resistance' trade-off. This technology was chosen in particular by Infineon for the realization of COOLMOS™ transistors [1] and by STMicroelectronics for the realization of MDMESH™ devices [2]. However, the manufacturing cost of this technology can be very high because the process requires a multiple epitaxy technique, resulting in a significant number of masks.…”

mentioning

confidence: 99%

An improved junction termination design using deep trenches for superjunction power devices

Noblecourt

Morancho

Isoird

et al. 2015

2015 22nd International Conference Mixed Design of Integrated Circuits &Amp; Systems (MIXDES)

View full text Add to dashboard Cite

Abstract-Among the numerous solutions developed to improve the handling capability of superjunction power devices, the Deep Trench Termination (DT 2 ) is the most adapted thanks to its lower cost and size compared to other technologies using the multiple epitaxy technique, and an easier implementation in the fabrication process. This paper presents the optimization of the Deep Trench Termination by means of TCAD 2D and 3D-simulations allowing the realization of deep trench superjunction devices (diodes and MOS transistors) for 1200 V applications. The work is focused on the influence of the dielectric passivation layer thickness and the field plate length on the breakdown voltage of a DT-SJDiode.

show abstract

“…Note that the model can also be used for the offset drain structure, being the MV structure with the thickness of the field oxide being zero. HV LDMOS transistors often have a graded doping profile in the drift region to fullfill the conditions of the RESURF principle [3], [4], or use superjunction techniques [5]. At present, these HV devices are very technology dependent, and it would be difficult to develop one general model for this type of device; this task is left for a succeeding research project.…”

mentioning

confidence: 99%

MOOSE: A Physically Based Compact DC Model of SOI LDMOSFETs for Analogue Circuit Simulation

D'Halleweyn

Benson

Redman-White

et al. 2004

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Abstract-In this paper, we present a compact model for silicon-on-insulator (SOI) laterally double diffused (LD) MOSFETs. The model is complete insofar as it uses no subcircuits, and is intended to predict device operation in all regions of bias. The device current is described by two main equations handling the MOS channel and the drift region, both of which are smooth and continuous in all operating regimes. Attention is also given to the modeling of inversion at the back oxide to ensure correct behavior is predicted for a source follower in power control applications ("high side operation"). A surface-potential-based formulation is used for the inversion/accumulation channel giving smooth transitions between different regions of operation, and care has been taken to ensure all expressions are smooth and infinitely differentiable to achieve the best possible convergence performance. Self (and coupled) heating effects exert a major influence over the behavior of power SOI devices, and these issues are incorporated in the model core in a consistent fashion.The model has been installed in a commercial SPICE-type circuit simulator and evaluated against individual devices and complete circuits fabricated in an industrial smart power SOI process. Accuracy is significantly improved with respect to the existing LDMOS models, and convergence behavior in switching and linear circuit simulations is comparable with industry standard models of this complexity.

show abstract

COOLMOS/sup TM/-a new milestone in high voltage power MOS

Cited by 194 publications

References 1 publication

Conception de transistors MOS haute tension (1 200 volts) pour l'électronique de puissance

Conception de transistors MOS haute tension (1 200 volts) pour l'électronique de puissance

An improved junction termination design using deep trenches for superjunction power devices

MOOSE: A Physically Based Compact DC Model of SOI LDMOSFETs for Analogue Circuit Simulation

Contact Info

Product

Resources

About