Coplanar amorphous silicon thin film transistor fabricated by inductively coupled plasma chemical vapor deposition

Abstract

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively coupled plasma (ICP) chemical vapor deposition (CVD) have been investigated. The ICP-CVD a-Si:H films deposited at the pressure of 30 mTorr exhibited the hydrogen content of 17 at. %, a photosensitivity of 106 at 100 mW/cm2 and a conductivity activation energy of 0.9 eV. A novel coplanar self-aligned a-Si:H thin film transistor was fabricated using Ni-silicide gate and source/drain electrodes. The simultaneous Ni-silicide formation of gate and source/drain regions using the stacked layers of thin a-Si:H, silicon nitride (SiNx) and a-Si:H reduces the offset length between gate and source/drain, which leads to the coplanar a-Si:H thin film transistor (TFT). This self-aligned a-Si:H TFT exhibited a field effect mobility of 0.44 cm2/V s, threshold voltage of 5.3 V and subthreshold slope of 0.5 V/dec. The coplanar geometry reduces the parasitic capacitance and parasitic resistance compared with those of conventional staggered a-Si:H TFTs.

Hydrogenated amorphous silicon thin-film transistor with a thin gate insulator

“…The parasitic capacitance between gate and source/drain should be as low as possible in order to reduce the line delay time and to reduce the kickback voltage [1]. To meet these requirements, the high on-state drain current and self-aligned, coplanar a-Si : H TFT's [2] are required.…”

“…In order to form Ni silicide, a 10-nm thick Ni layer was deposited by sputtering on the top of the a-Si : H. The Ni silicide with a 0741-3106/00$10.00 © 2000 IEEE sheet resistance of was formed by heating at 230 C for 1 h. The remaining nickel on the silicide was etched away using a (HNO 3 + HCl) solution. The fabrication process appears in the literature [2]. The ratio of channel width to length of the TFT was 65 m/28 m. × 10 F cm for 35-nm thick SiN x .…”

Copper gate hydrogenated amorphous silicon TFT with thin buffer layers

“…On the other hand, AlN is easily removed with a NaOH solution without causing any damage to the other layers after contact hole patterning. Finally, annealing the TFTs at 270 C for 120 min resulted in Ni-silicide layer on the n layer having a sheet resistance of around 3 [12], [13]. The ratio of channel width to length of the TFT was 39 m/5 m. Fig.…”

Leakage Current Reduction Techniques in Poly-Si TFTs for Active Matrix Liquid Crystal Displays: A Comprehensive Study

“…A and B paths show the thermionic field emission in the a-Si:H and poly-Si regions. It is worth noting that the leakage current of an a-Si:H TFT [71] is much smaller than that of a poly-Si. In other words, current "A" is much smaller than current "C." Therefore, the leakage current of the poly-Si TFT with a very thin a-Si:H buffer is smaller than that of the C-TFT.…”

“…A and B paths show the thermionic field emission in the a-Si:H and poly-Si region. It is worth noting that the leakage current of an a-Si:H TFT [71] is much smaller than that of a poly-Si. In other words, the current 'A' is much smaller than current 'C'.…”