Correlation between passivation film density and reliability of In–Ga–Zn–O thin-film transistors

Abstract

The effect of the film density of a SiO 2 passivation layer on the positive bias stress (PBS) stability of an In-Ga-Zn-O thin-film transistor (IGZO TFT) was investigated by a comparison of the results of the PBS test between ambient air and vacuum. The film density was varied by changing the deposition temperature. The TFT with low-density SiO 2 passivation exhibited a more severe threshold voltage shift (ΔV th ) under the PBS in ambient air than in vacuum. In contrast, no significant difference in ΔV th was observed from the TFT with a dense SiO 2 passivation. Thus, a dense passivation is essential for reducing ambient effects for IGZO TFTs.

Heterojunction channel engineering to enhance performance and reliability of amorphous In–Ga–Zn–O thin-film transistors

“…The effect of the deposition conditions of the SiO 2 passivation layer on the electrical properties of an IGZO111 TFT was reported previously. 53,54) After opening contact holes by photolithography and dry etching, a 40 nm thick ITO layer was deposited through a shadow mask to form source/drain (S/D) electrodes. Then, the TFTs were subjected to annealing in N 2 at 350 °C for 1 h. The channel length (L) and width (W) were 690 and 1000 μm, respectively.…”

Influence of a SiO2 passivation on electrical properties and reliability of In–W–Zn–O thin-film transistor

“…It has been known that the passivation layer for oxide TFTs played an important role because adsorption/desorption of oxygen and water molecules onto the exposed back-channel of the oxide TFTs cause long-term instability. [19][20][21] Although IWZO TFTs with passivation layer deposited by electron gun evaporation was reported by Ruan et al, 22) from the standpoint of the industrial applications, a plasma-enhanced chemical vapor deposition (PE-CVD) still have some advantage such as high throughput with an appropriate deposition rate and large area uniformity. Furthermore, there have been few reports for the influence of T a on transfer characteristics and reliability of the IWZO TFT with a passivation layer; nevertheless the oxygen deficiency related defects of the oxide semiconductor can be reduced by the annealing process.…”

“…Even under PBS, the TFT exhibited a huge positive V th shift (ΔV th ) of +28.2 V just after 1000 s. From previous studies, the origins of this huge positive ΔV th were assumed to be the adsorption of ambient molecules and electron trapping at gate insulator/channel interface. 2,[18][19][20][21] It is well known that higher T a eliminates the defects in the interface and bulk of the channel, and improves the reliability under PBS or positive bias temperature stress (PBTS). 2,18) However, the TFTs changed to conductors after annealing at 200 °C or higher as shown in Fig.…”