Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs

Chen, Ting‐Ju; Li, Jin-Fu; Tseng, Tsu-Wei

doi:10.1109/tcad.2011.2181510

Cited by 21 publications

(14 citation statements)

References 27 publications

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“…CRV has the same as the word width of the memory. Due to a large number of registers used in this method, the required consumption level is high [15]. In a memory with S R spare rows and…”

Section: Previous Bira Methodsmentioning

confidence: 99%

At-Speed Wordy-R-CRESTA Optimal Analyzer to Repair Word-Oriented Memories

Asli¹,

Khodadadi²,

Habiby³

2013

IJHIT

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“…CRV has the same as the word width of the memory. Due to a large number of registers used in this method, the required consumption level is high [15]. In a memory with S R spare rows and…”

Section: Previous Bira Methodsmentioning

confidence: 99%

At-Speed Wordy-R-CRESTA Optimal Analyzer to Repair Word-Oriented Memories

Asli¹,

Khodadadi²,

Habiby³

2013

IJHIT

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show abstract

“…These failures are persistent and uncorrectable, but generally can be detected (e.g., built-in self-test) after chip fabrication or by online test during usage. Then corresponding circuit or system level techniques (e.g., built-in self-repair) can be employed to tolerate them [ 77 , 78 ]. When employing MTJ in real applications, these failures should be seriously addressed to guarantee the product yield and reliability.…”

Section: Failure Tolerant Design Techniquesmentioning

confidence: 99%

“…Therefore, we can tolerate these hard failures based on the detection information (failure bit-map). One of the intuitive and direct techniques is to mask the hard failures with redundancy, which means replacing the cells (in hard failures) with good ones [ 78 , 79 ]. As shown in Figure 11 is an example to illustrate the concept.…”

Section: Failure Tolerant Design Techniquesmentioning

confidence: 99%

Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy

et al. 2016

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Magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy (PMA-MTJ) becomes a promising candidate to build up spin transfer torque magnetic random access memory (STT-MRAM) for the next generation of non-volatile memory as it features low spin transfer switching current, fast speed, high scalability, and easy integration into conventional complementary metal oxide semiconductor (CMOS) circuits. However, this device suffers from a number of failure issues, such as large process variation and tunneling barrier breakdown. The large process variation is an intrinsic issue for PMA-MTJ as it is based on the interfacial effects between ultra-thin films with few layers of atoms; the tunneling barrier breakdown is due to the requirement of an ultra-thin tunneling barrier (e.g., <1 nm) to reduce the resistance area for the spin transfer torque switching in the nanopillar. These failure issues limit the research and development of STT-MRAM to widely achieve commercial products. In this paper, we give a full analysis of failure mechanisms for PMA-MTJ and present some eventual solutions from device fabrication to system level integration to optimize the failure issues.

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“…Many BISR approaches and RA algorithms for various memory and redundancy architectures were proposed recently [2]- [7] that tried to balance the three parameters. Most common redundancy architecture targeted by these approaches is the non-block (traditional row/column) architecture [2], [3].…”

Section: Introductionmentioning

confidence: 99%

“…Memories are equipped with a number of redundant rows or columns (1-D redundancy) or both (2-D redundancy). When considering 2-D redundancy scheme, the problem of finding a repair solution is NP-complete [7]. If a fault is detected, whole row or column is used to replace it.…”

Section: Introductionmentioning

confidence: 99%

Redundancy algorithm for embedded memories with block-based architecture

Kristofik

Gramatova

2013

2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Built-in self-repair (BISR) is widely used to repair embedded memories within system on a chip (SoC) designs to improve their yield. One key component of the BISR circuit responsible for allocating redundancies is the redundancy analysis (RA) algorithm. One of the most important parameters used to evaluate RA algorithms is repair rate (the ratio of the number of the repaired memories to the number of faulty memories). In most BISR designs, redundancies are used on the row/column level. Some approaches target the block-based architecture where both memories and redundancies are divided into several blocks. Thus, allocation can be done on the block level and is more effective in terms of repair rate. These approaches, however, cannot guarantee optimal repair rate. In this paper, we propose a redundancy analysis algorithm for bitoriented memories with block-based redundancy architecture with optimal repair rate. Keywords-embedded memory; built-in redundancy analysis;repair rate; redundancy analysis algorithm.

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Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate for RAMs

Cited by 21 publications

References 27 publications

At-Speed Wordy-R-CRESTA Optimal Analyzer to Repair Word-Oriented Memories

At-Speed Wordy-R-CRESTA Optimal Analyzer to Repair Word-Oriented Memories

Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy

Redundancy algorithm for embedded memories with block-based architecture

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