Coupling-driven bus design for low-power application-specific systems

Shin, Youngsoo; Sakurai, Takayasu

doi:10.1145/378239.379059

Cited by 69 publications

(61 citation statements)

References 16 publications

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“…The approaches in [5,6,7,8] seek to minimize the dynamic power and delay in buses through various encoding schemes. The work in [5] is well suited for delay reduction by elimination of crosstalk (through a "selfshield encoding") but it does not address power reduction.…”

Section: Introductionmentioning

confidence: 99%

“…However, they do not address the critical issue of static leakage power. In [7], the authors shuffle the order of the bus lines to minimize oppositephase transitions on adjacent bus lines to reduce power due to crosstalk. The results in [8] show a reduction in both static and dynamic power using their technique of low-voltage BiCMOS and termination networks.…”

Section: Introductionmentioning

confidence: 99%

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Leakage-and crosstalk-aware bus encoding for total power reduction

Deogun

Rao

Sylvester

et al. 2004

Proceedings of the 41st Annual Design Automation Conference

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Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We introduce a new buffer design approach with selective use of high threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Leakage-and crosstalk-aware bus encoding for total power reduction

Deogun

Rao

Sylvester

et al. 2004

Proceedings of the 41st Annual Design Automation Conference

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show abstract

“…Another approach is introduced by Kim et al [4] where a couplingsensitive invert scheme is introduced leading to around 30% power savings. The work of Shin/Sakurai [9] presents a coupling driven bus encoder that capitalizes on the fact that the data sent via the bus might be known a priori. They report for those cases up to 46% energy savings.…”

Section: Related Workmentioning

confidence: 99%

ETAM++: extended transition activity measure for low power address bus designs

Lekatsas¹,

Henkel²

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conferen

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“…All the above three approaches assume a known input vector (and thus suffer from pattern dependence) and essentially replace the circuit simulation step in the simulative techniques. [9,21] take a switch factor based approach to model capacitive coupling. [9] incorrectly assumes the worst-case switch factor to be one, and also assumes all lines to be transitioning simultaneously.…”

Section: Introductionmentioning

confidence: 99%

“…[9] incorrectly assumes the worst-case switch factor to be one, and also assumes all lines to be transitioning simultaneously. [21] essentially modifies activity factors of lines to take into account neighbor switching.. Effect of slew times and switching windows is ignored. Moreover, it is not clear how the switching correlation between lines is being estimated.…”

Section: Introductionmentioning

confidence: 99%

Quantifying error in dynamic power estimation of CMOS circuits

Gupta

Kahng²

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.

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Conventional power estimation techniques are prone to many sources of error. With increasing dominance of coupling capacitances, capacitive coupling potentially contributes significantly to UDSM power consumption. We analyze potential sources of inaccuracy in power estimation, focusing on those due to coupling. Our results suggest that traditional power estimates can be off by as much as 50%. IntroductionThe advent of low-power portable devices along with continued increases in device density and operating frequency make power consumption a major concern in modern VLSI design. In this work, we seek to identify sources of error in power estimation, focusing on those which arise if effects of capacitive coupling are ignored. Our aim is not to propose new coupling-aware power estimation techniques but rather to quantify the error in noncoupling aware methods. Here, "ignoring" coupling includes ignoring crosstalk noise, as well as ignoring neighbor switching and its effect on effective value of coupling capacitance.Capacitive switching, leakage, short-circuit current and standby current are the sources of power consumption. Static power refers to the sum of leakage and standby power while dynamic power is the sum of short-circuit and switching power 1 . In this work, we concern ourselves with dynamic power consumption and capacitive switching in particular. Power estimation approaches can be classified into two categories, as follows.• Simulative Techniques. These techniques employ direct simulation or statistical sampling techniques. Issues such as hazard generation and propagation, or reconvergent fanoutinduced correlations, are automatically taken into consideration. If performed after layout and parasitic extraction, accurate estimation of capacitances (including coupling) and their effects is possible. A circuit simulator such as HSpice [10] or Powermill [18] is used for estimation of average power. A gate-level HDL simulation using tools such as NC-Verilog can also be adapted to report power dissipation using power models of gates from the library.• Probabilistic Techniques. To avoid the strong pattern dependence and huge running times of simulation-based approaches, probabilistic approaches are used. These calculate probabilities of switching activity for each circuit node and multiply by CV 2 dd to obtain the node's energy consumption. This dynamic capacitive power is summed up over all nodes to obtain total energy consumption of the circuit. The transition probability of each gate is sometimes referred to as the * This research was supported in part by the MARCO Gigascale Silicon Research Center and Cadence Design Systems, Inc.1 There may be some clash of terminology here as the term dynamic power is sometimes used to refer to total instantaneous peak power rather than the time averaged power we use it for. We use the terminology presented in [17]. activity factor [3,7].[8] predicts constant activity factor of 0.15 through all technology nodes.Except for transistor-level simulation, typical power es...

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Coupling-driven bus design for low-power application-specific systems

Cited by 69 publications

References 16 publications

Leakage-and crosstalk-aware bus encoding for total power reduction

Leakage-and crosstalk-aware bus encoding for total power reduction

ETAM++: extended transition activity measure for low power address bus designs

Quantifying error in dynamic power estimation of CMOS circuits

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