Crosstalk Reduction in Mixed-Signal 3-D Integrated Circuits With Interdevice Layer Ground Planes

Kim, S.K.; Liu, C.C.; Xue, Lei; Tiwari, Sandip

doi:10.1109/ted.2005.850641

Cited by 17 publications

(5 citation statements)

References 20 publications

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“…Previous works have highlighted this vertical electrical interference issue between interconnects and devices [9] in different tiers with measured results, and placing conductive thin films between tiers for interference screening (Fig. 8d) has been proposed [68]. In this work, to minimally impact the 3D-IC thickness, we propose to use a layer of 2D metallic material (e.g., graphene) in ILD (as backgate or shielding layer, Fig.…”

Section: Electrical Interference and Their Screening By 2d Materialsmentioning

confidence: 99%

“…The scattering parameter S 21 , which describes the power transferred from one tier to the other, was used to quantify coupling between adjacent tiers and simulations predict that screening effects will be negligible when screening layer thickness is reduced to 1 nm in previous studies [68]. This is because, under quasistatic approximation (the geometries are much smaller than the wavelength in the frequency range under study), although the electric field is effectively screened by the conductive layer, the magnetic field leaks through it, which causes power transmission through inductive coupling.…”

Section: B High-frequency Electric Field Screeningmentioning

confidence: 99%

See 1 more Smart Citation

Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges

Jiang

Parto

Cao

et al. 2019

IEEE J. Electron Devices Soc.

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As a possible pathway to continue Moore's law indefinitely into the future as well as unprecedented beyond-Moore heterogeneous integration, we examine the prospects of building monolithic 3D integrated circuits (M3D-IC) with atomically-thin or 2D van der Waals materials in terms of overcoming the major drawbacks of current 3D-ICs, including low process thermal budget, inter-tier signal delay, chip-overheating, and inter-tier electrical interference problems. Our holistic evaluation includes consideration of the electrical performance, thermal issues, and electromagnetic interference as well as attention to the synthesis methods necessary for low-temperature transfer-free 2D materials growth in M3D fabrication. Both in-plane and out-of-plane heat-dissipation in 3D-ICs made with 2D materials are evaluated and compared with those of bulk materials. Electrostatic and high-frequency electric-field simulations are conducted to assess the screening effect by graphene and effect of scaling down the inter-layer dielectric (ILD) thickness. Our analysis reveals for the first time that the 2D-based M3D integration can offer >ten-folds higher integration density compared with through-silicon-via (TSV)-based 3D integration, and >150% integration density improvement with respect to conventional M3D integration. Therefore, 2D materials provide a significantly better platform, with respect to bulk materials (such as Si, Ge, GaN), for realizing ultra-high-density M3D-ICs of ultimate thinness for next-generation electronics. INDEX TERMS 3D integration, 2D layered materials, h-BN, MoS 2 , WSe 2 , beyond-Moore integration, electromagnetic interference, graphene, interconnect, interface thermal conductivity, Moore's law, thermal profile, vertically-stacked devices.

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Section: Electrical Interference and Their Screening By 2d Materialsmentioning

confidence: 99%

Section: B High-frequency Electric Field Screeningmentioning

confidence: 99%

Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges

Jiang

Parto

Cao

et al. 2019

IEEE J. Electron Devices Soc.

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show abstract

“…In mixedsignal systems, noise-sensitive analog/RF circuitry is prone to failure due to interference from their digital counterpart through the base silicon substrate. Three-dimensional integration aids in the solution for noise isolation as it separates the analog/RF and digital circuits into different substrates, with the metal or the dielectric bonding layer used in wafer-bonding technology providing an effective guard ring [5]. The final footprint of the packaged system can also be smaller for a 3-D implementation.…”

Section: Introductionmentioning

confidence: 99%

Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints

Weerasekera

Pamunuwa

Zheng

et al. 2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Present day market demand for high-performance high-density portable hand-held applications has shifted the focus from 2-D planar system-on-a-chip-type single-chip solutions to alternatives such as tiled silicon and single-level embedded modules as well as 3-D die stacks. Among the various choices, finding an optimal solution for system implementation deals usually with cost, performance, power, thermal, and technological tradeoff analyses at the system conceptual level. It has been estimated that decisions made in the first 20% of the design cycle influence up to 80% of the final product cost. In this paper, we discuss realistic metrics appropriate for performance and cost tradeoff analyses both at the system conceptual level in the early stages of the design cycle and in the implementation phase, for verification. In order to validate the proposed metrics and methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and the performance tradeoffs discussed. This case study is used to highlight the importance of a cost and performance tradeoff analysis early in the design flow.Index Terms-Die stacking, performance and cost tradeoffs, power consumption, system-in-package (SiP), system-on-chip (SoC), system-on-package (SoP), thermal analysis, wafer-level integration (WLI), 3-D integration.

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“…In mixed-signal systems, Noise-sensitive analog/RF circuitry is prone to failure due to interference from their digital counterpart through the base silicon substrate. 3-D integration aids in the solution for noise isolation since it separates the analog/RF and digital circuits into different substrates with the metal or the dielectric bonding layer used in wafer-bonding technology [5] providing an effective guard ring. The final footprint of the packaged system is also less for a 3-D implementation.…”

Section: Introductionmentioning

confidence: 99%

Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs

Weerasekera¹,

Zheng²,

Pamunuwa³

et al. 2007

2007 IEEE/ACM International Conference on Computer-Aided Design

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Because of the today's market demand for highperformance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result upto 80% of the final product cost.In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them.

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Crosstalk Reduction in Mixed-Signal 3-D Integrated Circuits With Interdevice Layer Ground Planes

Cited by 17 publications

References 20 publications

Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges

Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges

Two-Dimensional and Three-Dimensional Integration of Heterogeneous Electronic Systems Under Cost, Performance, and Technological Constraints

Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs

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