Decimal to Excess-3 and Excess-3 to Decimal Code Converters in QCA Nanotechnology

Fouladinia, Farhad; Gholami, Mohammad

doi:10.21203/rs.3.rs-2218039/v1

Cited by 7 publications

(7 citation statements)

References 13 publications

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“…The electric field distribution of the proposed undoped HEMT structure under the 5 nm regime gate with HfO2 is shown in Figure 10. The undoped HEMT electric field concentration improved compared to conventional devices [30].…”

Section: Resultsmentioning

confidence: 93%

Performance Analysis of High-K Dielectric Heterojunction High Electron Mobility Transistor for RF Applications

Radhamma¹,

Chary²,

Krishnamurthy³

et al. 2023

IJE

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We have designed and simulated a 10-nanometer regime gate High Electron Mobility Transistor (HEMT) with an undoped region (UR) under the gate with high k dielectric as hafnium oxide (HfO2). The thickness of metal gate(G) and undoped regions are equal but length of channel(C) is not equivalent. The proposed Undoped under the gate dielectric High Electron Mobility Transistor reduces the maximum electric field(V) in the channel region and increases the drain current significantly. The High-K dielectric High Electron Mobility Transistor structure obtained a saturated Ion current of 60% higher than the conventional structure. For High critical Power and High-frequency Power transmission Amplifiers utilizes the AlGaN/GaN/SiC-based High Electron Mobility Transistor with an undoped region under the gate with High-K Hafnium oxide. The Proposed advanced High Electron Mobility Transistor Produces a higher Drain current (Id), 54% high transconductance (Gm) with Low On-Resistance (Ron), and High conductivity in comparison to typical High Electron Mobility Transistor. In Addition to these improved characteristics, the Electric field along the Y direction is also observed. The proposed structure formed by Low-k Dielectric materials in the process of Silicon Dioxide(SiO2) and High-k dielectric being Titanium Dioxide (TiO2) and Hafnium Oxide (HfO2) created more opportunities in Power electronics and radio frequency operations.

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Section: Resultsmentioning

confidence: 93%

Performance Analysis of High-K Dielectric Heterojunction High Electron Mobility Transistor for RF Applications

Radhamma¹,

Chary²,

Krishnamurthy³

et al. 2023

IJE

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“…In particular, TFET demonstrates diverse voltage shifts during its interaction with different biological molecules that have distinct K values. In this study, the changes in biomolecule (such as K=1,K=3,K=7) biomolecule affect the potential across the TFET (28,29). The variation of dielectric constant of the immobilized biomolecule significantly affects the local electric field in nano cavity of the TFET.…”

Section: Resultsmentioning

confidence: 95%

Design and Performance Analysis of Gate Overlap Dual Material Tunnel Field Effect Transistor

Buttol,

Balaji

2024

IJE

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This study introduces a biosensor employing a dielectric-modulated dual material gate tunnel field effect transistor (DM-DMG TFET) in 10 nanometer technology. To detect diverse bio molecules, the biosensor incorporates a nano gap cavity formed through gate overlap on the drain side. The variation in ambipolar current serves as the sensing parameter, influenced by altering the dielectric constants of immobilized bio molecules within the nano cavity. In this paper, the simulation results of biosensor employing a dielectric-modulated dual material gate tunnel field effect transistor with different dielectric constants imposed in nano cavity. A comprehensive examination of the biosensor's performance is conducted, exploring various positions and filling factors of bio molecules within the nano cavity region. This analysis involves a thorough investigation into the device's performance, considering a range of parameters such as drain current, electric field distribution, variations in surface potential, configurations of energy bands, behaviors of carrier concentration, and the Ion/Ioff ratio. The simulations are done using the Silvaco TCAD Atlas tool.

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“…As 𝑉𝑑𝑠 increases beyond Vth, the transistor enters the saturation region. In this region, the drain current becomes relatively independent of 𝑉𝑑𝑠 (29,30).…”

Section: Drain Current Vs Drain Voltage Characteristicsmentioning

confidence: 99%

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Padmaja,

Vemana Chary,

Erigela

et al. 2024

IJE

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A High-K Dielectric Dual Metal Gate FinFET (DMG-FinFET) is proposed in this work to improve the drain current and electrical characteristics of the device. The proposed device employing dielectric materials such as Silicon dioxide, Hafnium oxide and Titanium oxide and investigated in 10 nm technology. The architecture represents a critical advancement in transistor design, addressing challenges posed by traditional high-K gate dielectric materials being HfO2 and TiO2. This work employs a comprehensive approach, incorporating simulation techniques to evaluate the performance metrics of DMG FinFET. This investigation encompasses key aspects being transistor characteristics, power consumption, and reliability. This high-k dielectric (HfO2) Dual material Gate -FinFET device achieving improved performance parameters such as Ion= 32.12 mA, Ioff= 33 μA, Gm(max) = 0.045 S, Gds(max) = 0.024 S and Ron(max) = 32.87 kΩ. Therefore this work is suitable for designing high performance devices with high-k dielectric materials being HfO2 and TiO2. The impact of dual metal gate materials on Ion, Ioff, Gm (max), Gds(max) and Ron(max) is calculated and improved 64% compared to conventional device.

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Decimal to Excess-3 and Excess-3 to Decimal Code Converters in QCA Nanotechnology

Cited by 7 publications

References 13 publications

Performance Analysis of High-K Dielectric Heterojunction High Electron Mobility Transistor for RF Applications

Performance Analysis of High-K Dielectric Heterojunction High Electron Mobility Transistor for RF Applications

Design and Performance Analysis of Gate Overlap Dual Material Tunnel Field Effect Transistor

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

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