Dedicated module access in dynamically reconfigurable systems

Abstract

Modern FPGAs, such as the Xilinx Virtex-II Series, offer the feature of partial and dynamic reconfiguration, allowing to load various hardware configurations (i.e., HW modules) during run-time. To enable communication with these modules and for controlling purposes, dedicated access to each module as well as dedicated signals to control the global communication are required. This paper discusses several ways of implementing dedicated signals and addresses the impact on dynamically reconfigurable systems. Two new approaches are introduced, which allow a permanent access to the modules and to the communication infrastructure even during reconfiguration.

Design Optimizations for Tiled Partially Reconfigurable Systems

“…An inhomogeneous communication infrastructure can significantly reduce the number of feasible positions of the PR modules. In order to maintain the homogeneity of the communication infrastructures, the implementation of dedicated signals requires special design concepts introduced in [1] and [27]. Fig.…”

Obstacle-free two-dimensional online-routing for run-time reconfigurable FPGA-based systems

“…The difficulty has its origin in a weak tool support in order to exactly control the implementation of the routing on an FPGA. For providing a 2D circuit switching networks that are capable of integrating reconfigurable modules, macro-based communication architectures have been proposed in [4], [5], [6]. In macro-based on-FPGA communication architectures, logic and routing resources of the FPGA fabric are used to link and route signal paths among reconfigurable modules and the static system.…”

“…Opposed to previous systems, where the switching is carried out using look-up tables ( [4], [5], [6], [7]) or done in exclusively reserved tiles ( [8]), we propose to implement the switching elements directly within a exclusively allocated subset of switch matrix resources together with the module implementation. In this approach, we strictly separate FPGA resources for either implementing modules or for providing top level routing among a set of partial modules (or the static system).…”

Efficient Reconfigurable On-Chip Buses for FPGAs

“…A suitable bus infrastructure for integrating reconfigurable modules should be able to connect modules of different sizes efficiently to the system. In [3], a more flexible approach is presented that uses onchip tristate drivers in order to build buses for reconfigurable systems. In addition, [3] presented different approaches for distributing dedicated signals to the modules connected to the bus.…”

“…In [3], a more flexible approach is presented that uses onchip tristate drivers in order to build buses for reconfigurable systems. In addition, [3] presented different approaches for distributing dedicated signals to the modules connected to the bus. These approaches were either inflexible in terms of module relocation and multiple instantiation or came along with a significant area overhead or signal latency.…”