Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything?

Moore, W. G.; Gronthoud, G.; Baker, K.; Lousberg, M.

doi:10.1109/test.2000.894196

Cited by 37 publications

(22 citation statements)

References 24 publications

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“…These bridges typically have a bridge resistance that is outside the range that can be detected by logic testing. An analysis of delay fault testing targeting resistive bridges was performed in [66,67]. Other studies have recommended IDDQ testing for bridging faults [48,68], because the active bridge allows a current to flow from the supply voltage rail, through the gate that is driving high, through the defect and through the gate that is driving low to the ground rail.…”

Section: Testing For Bridge Defectsmentioning

confidence: 99%

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Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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The final part studies the impact of process variation on the behaviour of bridge defects.Detailed analysis using synthesised ISCAS benchmarks and realistic bridge model shows that process variation leads to additional faults. If process variation is not considered in test generation, the test will fail to detect some of these faults, which leads to test escapes. A novel metric to quantify the impact of process variation on test quality is employed in the development of a new test generation tool, which achieves high bridge defect coverage. The method achieves a user-specified test quality with test sets which are smaller than test sets generated without consideration of process variation.

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Section: Testing For Bridge Defectsmentioning

confidence: 99%

“…Capacitive coupling to neighbouring nets, as considered in the model, causes the victim net voltage to vary with the signal on a neighbouring net [67]. If the neighbouring node is down-stream from the victim net, i.e.…”

Section: Capacitive Coupling Modelmentioning

confidence: 99%

Investigation into voltage and process variation-aware manufacturing test

Ingelsson

Al-Hashimi

2011

2011 IEEE International Test Conference

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“…The behaviour of the circuit will depend mainly on the value of the resistance as well as the supply voltage [1]. The critical resistance is the value which divides these two classes of open defects [9].…”

Section: A Resistive Open Defectsmentioning

confidence: 99%

Delay fault modelling/simulation using VHDL-AMS in multi-Vdd systems

Ali

Zwoliński

Ahmadi

2008

2008 26th International Conference on Microelectronics

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Abstract-With the growing density of Very Large Scale Integrated(VLSI) circuits, traditional digital fault simulation is no longer a viable option. This is because of analogue-like behaviour in digital circuits. The need for fast fault simulation is one of the main requirements in test pattern generation. The trade off between accurate simulations at transistor level, as in SPICE and fast simulation at gate level using a Hardware Descriptive Language (HDL) can be achieved by using behavioural modelling languages such as VHDL-AMS. In this paper, we have demonstrated that behavioural fault simulation for resistive faults can produce fast and accurate results.

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“…From a reliability and quality-engineering standpoint, weak opens are potential hazards because they can escape the Boolean testing stage. [7][8][9][10] To detect weak opens, engineers must apply more sophisticated test methods, such as delay fault testing. To substantiate the need for such tests, later in the article we show a positive correlation between the distribution of weak opens found in back-end defect monitors and the number of delay faults found in a small test chip.…”

mentioning

confidence: 99%