Dependency of Tunneling Field-Effect Transistor(TFET) Characteristics on Operation Regions

Lee, Min Jin; Choi, Woo Young

doi:10.5573/jsts.2011.11.4.287

Cited by 11 publications

(9 citation statements)

References 13 publications

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“…This agrees to Lee and Choi's result showing the pre-dominance of tunneling resistance in their study. 28) Another interesting point is the saturation drain bias V DS,sat also increases as I D decreases with an increase of the source side spacer length. Considering that an increase of L spacer,D does not influence V DS,sat , the slow saturation of I D under a small drain bias is judged to be a phenomenon associated with the source-side tunneling resistance.…”

Section: Gate Bias (Linear Scale) Drain Current (Log Scale)mentioning

confidence: 99%

Complementary-Metal–Oxide–Semiconductor Technology-Compatible Tunneling Field-Effect Transistors with 14 nm Gate, Sigma-Shape Source, and Recessed Channel

Sun

Kim

et al. 2013

Jpn. J. Appl. Phys.

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A new design of tunneling field-effect transistor (TFET) focusing on the compatibility to the current Si complementary-metal–oxide–semiconductor (CMOS) technology is proposed. In addition to use of the structural components of the state-of-the-art CMOS technologies, such as Σ-shaped embedded SiGe and the replacement gate techniques, two-step sidewall image transfer gate-patterning and channel recess process are adopted to form highly-scaled nanoscale TFET. Process integration scheme and the expected device characteristics are examined on the basis of technology computer-aided design (TCAD) simulation on 14-nm-gate model devices. Tunability of transfer characteristics with doping around tip region, control of short-channel effect with channel recess, and improvement of current drivaility with SiGe composition are studied. Design of the source region is found to be critical in controlling the current drivability of the device and output characteristics.

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Section: Gate Bias (Linear Scale) Drain Current (Log Scale)mentioning

confidence: 99%

Complementary-Metal–Oxide–Semiconductor Technology-Compatible Tunneling Field-Effect Transistors with 14 nm Gate, Sigma-Shape Source, and Recessed Channel

Sun

Kim

et al. 2013

Jpn. J. Appl. Phys.

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“…The use of tunneling field-effect transistors (TFETs) is one of the solutions owing to their excellent subthreshold swing (S) and low off-state current (I off ). [1][2][3][4][5][6][7][8][9][10] In spite of these advantages, low on-state current (I on ) and operation speed have been pointed as the drawbacks of silicon (Si) TFETs. I on can be significantly improved by introducing a new channel material, doping profiling, and varying gate dielectric in various combinations.…”

Section: Introductionmentioning

confidence: 99%

Compound Semiconductor Tunneling Field-Effect Transistor Based on Ge/GaAs Heterojunction with Tunneling-Boost Layer for High-Performance Operation

Yoon

Cho

Seo

et al. 2013

Jpn. J. Appl. Phys.

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In this work, a high-performance compound semiconductor tunneling field-effect transistor (TFET) based on germanium (Ge)/gallium arsenide (GaAs) heterojunction with a tunneling-boost layer is investigated. The tunneling-boost layer in the source-side channel alters the energy band-gap structure between the source and the channel, which affects current drivability considerably. It is shown that controlling the lengths of the boosting layer (thin n+ GaAs layer) and lightly doped p-type channel (p-GaAs) also has substantial effects on adjusting V th without complications arising from shifting metal workfunction. Furthermore, we evaluate device performances such as on-state current (I on), subthreshold swing (S), intrinsic delay time (τ), and cut-off frequency (f T). The proposed TFET with an n-GaAs length of 12 nm showed an S of 27 mV/dec and approximately 3 times higher I on than that of the device without a boosting layer. Moreover, it is confirmed from the extracted excellent radio-frequency (RF) parameters that the proposed device is suitable for RF applications.

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“…Fig. 9 shows that RUTFET has excellent scalability without any degradation of SS and draininduced barrier thinning (DIBT) [29,30,31,32,33] since its main channel length is defined along with vertical direction. Moreover, the I OFF slightly decrease due to the decrease of SRH (Shockley-Read-Hall) current while I ON increases with the help of reduced channel resistance (R CH ).…”

Section: Scalability Of Rutfetmentioning

confidence: 99%

“…5 shows the effect of L SD (i.e., length of intrinsic source/drain between PGs and CG) on transfer characteristics. In case of RUTFET, L SD is corresponded to the tunneling barrier width (W TUN ) which is a dominant factor for SS as well as drain current (I D ) [33]. If L SD decrease, the BTBT rate is exponentially increased which contributes to improvements of SS and I ON (inset of Fig.…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable U-shaped tunnel field-effect transistor

Lee

kwon

Choi

et al. 2017

IEICE Electron. Express

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A reconfigurable U-shaped tunnel field-effect transistor (RUT-FET) is proposed as a low-power dynamically programmable logic device. It has several advantages over conventional reconfigurable TFETs: 1) Excellent scalability without any degradation of subthreshold swing (SS) and draininduced barrier thinning (DIBT) with recessed channel structure. 2) High current drivability with increased band-to-band tunneling junction 3) Scaling of SS with tunneling barrier width defined by geometrical parameters. In this manuscript, its electrical characteristics are examined by technology computer-aided design (TCAD) simulation. It shows ∼30× higher ON-state current than control devices and 41.8 mV/dec-SS during drain current increase by five orders magnitude. The reconfigurable operations for nand p-type FETs are also discussed.

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Dependency of Tunneling Field-Effect Transistor(TFET) Characteristics on Operation Regions

Cited by 11 publications

References 13 publications

Complementary-Metal–Oxide–Semiconductor Technology-Compatible Tunneling Field-Effect Transistors with 14 nm Gate, Sigma-Shape Source, and Recessed Channel

Complementary-Metal–Oxide–Semiconductor Technology-Compatible Tunneling Field-Effect Transistors with 14 nm Gate, Sigma-Shape Source, and Recessed Channel

Compound Semiconductor Tunneling Field-Effect Transistor Based on Ge/GaAs Heterojunction with Tunneling-Boost Layer for High-Performance Operation

Reconfigurable U-shaped tunnel field-effect transistor

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