Deposition-Temperature Effect on Nitride Trapping Layer of Silicon–Oxide–Nitride–Oxide–Silicon Memory

Wu, Jialin; Kao, Chin-Hsing; Chien, Hua-Ching; Wu, Cheng-Yen; Wang, Je-Chuang

doi:10.1143/jjap.46.2827

Cited by 4 publications

(3 citation statements)

References 10 publications

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“…In this 0018-9383/$26.00 © 2010 IEEE paper, a SONOS-type Flash memory with in situ embedded Si-NCs in silicon nitride is fully investigated in detail, including dot size and density analyzed by AFM and transmission electron microscopy (TEM). The performance and reliability of devices formed with different Si-NC deposition times (10,30, 60, and 90 s), including data retention, multilevel and 2-b operation, P/E cycling test, and drain and gate disturbance, were investigated. Fig.…”

Section: Introductionmentioning

confidence: 99%

Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

Chiang

Cheng-Yu

et al. 2010

IEEE Trans. Electron Devices

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Section: Introductionmentioning

confidence: 99%

Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

Chiang

Cheng-Yu

et al. 2010

IEEE Trans. Electron Devices

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“…With continued-scaling down, the number will decrease even further, which means that reliability will become even more important. To maintain the reliability of this technology, it is important to have not only a technical understanding of device structures, operational principles, [5][6][7][8] and materials 9,10) but also an understanding from a manufacturing technology viewpoint. In SONOS 2-bit storage flash memory, we discovered a case of noncycled charge loss (charge loss) that is dependent on the distance between contact windows and word lines (WLs) and is further dependent on the conditions of thermal treatment after the formation of contact windows.…”

Section: Introductionmentioning

confidence: 99%

Mobile-Ion-Induced Charge Loss Failure in Silicon–Oxide–Nitride–Oxide–Silicon Two-Bit Storage Flash Memory

Imaoka¹,

Higashi²,

Shiraiwa³

et al. 2009

jjap

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In standard quantum mechanics, it is not possible to directly extend the Schrödinger equation to spinors, so the Pauli equation must be derived from the Dirac equation by taking its non-relativistic limit. Hence, it predicts the existence of an intrinsic magnetic moment for the electron and gives its correct value. In the scale relativity framework, the Schrödinger, Klein-Gordon and Dirac equations have been derived from first principles as geodesics equations of a non-differentiable and continuous spacetime. Since such a generalized geometry implies the occurrence of new discrete symmetry breakings, this has led us to write Dirac bi-spinors in the form of bi-quaternions (complex quaternions). In the present work, we show that, in scale relativity also, the correct Pauli equation can only be obtained from a non-relativistic limit of the relativistic geodesics equation (which, after integration, becomes the Dirac equation) and not from the non-relativistic formalism (that involves symmetry breakings in a fractal 3-space). The same degeneracy procedure, when it is applied to the bi-quaternionic 4-velocity used to derive the Dirac equation, naturally yields a Pauli-type quaternionic 3-velocity. It therefore corroborates the relevance of the scale relativity approach for the building from first principles of the quantum postulates and the quantum tools. This also reinforces the relativistic and fundamentally quantum nature of spin, which we attribute in scale relativity to the non-differentiability of the quantum spacetime geometry (and not only of the quantum space). We conclude by performing numerical simulations of spinor geodesics, that allow one to gain a physical geometric picture of the nature of spin.

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“…The erasing speed of N-rich SiN trapping layer device is not fast as well because N-rich SiN has shallower hole trap. Furthermore, it is known that SiN deposited at lower temperature(600°C) has lower bandgap and shallower trap level [2]. But the effects of N-rich SiN and low temperature N-rich SiN (LT N-rich SiN) for tunneling oxide stack are rarely reported.…”

mentioning

confidence: 99%

Improved characteristics of charge-trapping flash device with tunneling layer formed by low temperature nitrogen-rich SiN/SiO<inf>2</inf> stack

Chen

Chang‐Liao

et al. 2011

2011 International Semiconductor Device Research Symposium (ISDRS)

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For better performance on charge-trapping(CT) flash device, tunneling layer stacks of nitrogen(N)-rich SiN/SiO 2 and low temperature(LT) N-rich SiN/SiO 2 are studied. The programming and erasing speeds of CT flash device are significantly improved by the tunneling layer stacks due to the lower conduction and valence band offsets of N-rich and LT N-rich SiN. The retention properties of CT flash devices with standard SiN trapping layer are satisfactory. Introduction: Recently, nitride-based flash device has attracted great interest for nonvolatile memory applications. It is widely applied to portable electronic products such as smart phone and laptop PC. For the need of higher device density, some 3D device structures have been proposed [1], and they are all based on silicon nitride (SiN) trapping layer. CT flash devices are greatly influenced by the process parameters of SiN layer. However, only Si-rich SiN used as trapping layer is commonly reported. With smaller bandgap, the erasing speed of Si-rich SiN trapping layer device is faster than that of standard SiN trapping layer device. The erasing speed of N-rich SiN trapping layer device is not fast as well because N-rich SiN has shallower hole trap. Furthermore, it is known that SiN deposited at lower temperature(600°C) has lower bandgap and shallower trap level [2]. But the effects of N-rich SiN and low temperature N-rich SiN (LT N-rich SiN) for tunneling oxide stack are rarely reported. In this work, the tunneling layer stacks of Nrich SiN/SiO 2 and LT N-rich SiN/SiO 2 on CT flash device are studied. Different trapping layer (standard SiN and Si-rich SiN) are compared as well. Experimental: Flash capacitors were fabricated on p-type Si (100) wafer. Samples with two different trapping layers, standard SiN and Si-rich SiN, divide all the samples into two parts. In each part, the effects of tunneling layers composed of simply SiO 2 , N-rich SiN/SiO 2 , and LT Nrich SiN/SiO 2 are compared. The fabrication process and structure graph are shown in Fig. 1. Note that SiO 2 and SiN were all formed by RTO and LPCVD, respectively. Split table and detailed LPCVD SiN process parameter are listed in Table 1 and Table 2, respectively. Results and Discussion: The programming and erasing (P/E) speeds of samples with standard SiN trapping layer are shown in Fig. 2 and Fig. 3, respectively. It can be seen that the P/E speeds of stacked tunneling layer samples are faster than that of single tunneling layer one. This is because the conduction and valence band offsets of N-rich and LT N-rich SiN are smaller than that of SiO 2 , resulting in a shorter tunneling length of the stacked layer seen by carriers [3]. The P/E speeds of LT N-rich SiN/SiO 2 stacked sample are faster than that of N-rich SiN/SiO 2 stacked one. This is because the bandgap for low temperature deposited SiN is smaller. The retention performance of stacked tunneling layer samples becomes a little worse as shown in Fig. 4 while higher erasing speed is achieved. This is because electrons in trapping layer are easier t...

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Deposition-Temperature Effect on Nitride Trapping Layer of Silicon–Oxide–Nitride–Oxide–Silicon Memory

Cited by 4 publications

References 10 publications

Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

Characteristics of SONOS-Type Flash Memory With In Situ Embedded Silicon Nanocrystals

Mobile-Ion-Induced Charge Loss Failure in Silicon–Oxide–Nitride–Oxide–Silicon Two-Bit Storage Flash Memory

Improved characteristics of charge-trapping flash device with tunneling layer formed by low temperature nitrogen-rich SiN/SiO<inf>2</inf> stack

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